Timing closure on cloned clock gate enable inputs

Our IP has a software controlled clock gate controlling an entire clock domain (several hundred flops). I noticed that in some cases, the clock gate is cloned post CTS, which create a large fanout path from the enable to the different clones. This path fails then fails timing checks. Apologies if this should not come as a surprise; I'm mostly a Verilog guy.

I have searched quite a lot online but could not find a reliable method of dealing with this kind of problem. The only method that could seemingly solve this is a set_max_fanout/set_register_duplication directive on the enable flop, but for reasons that people online do not explain, backend engineers do not like to use these directives. So:

1. Is there an industry-standard way to deal with this kind of problems? 
2. Can anyone tell me why set_max_fanout/set_register_duplication directives are frowned upon?

I have some ideas regarding 1 but they usually involve severe limits on the users to configure clock gating only within a reset context.

Many thanks in advance!