Custom IC Design

Latest Posts

Discussion

Guidelines for the Custom IC Design Forum

Category: Custom IC Design

By Andrew Beckett
•
started over 13 years ago

0 replies • 27167 views
Discussion

VIVA: Change color/disable highlighting around current (sub-)window

Category: Custom IC Design

By dontpanic
•
updated 2 hours ago by dontpanic

6 replies • 137 views
Discussion

spectre assert

Category: Custom IC Design

By Joe Mellon
•
updated 2 hours ago by Andrew Beckett

1 replies • 39 views
Discussion

information about (description of) gsclib045 components?

Category: Custom IC Design

By GS202507021424
•
updated 5 hours ago by Andrew Beckett

1 replies • 60 views
Discussion

The current direction is different after simulation with different fingers of the same mos

Category: Custom IC Design

By dogman4
•
updated 7 hours ago by dogman4

1 replies • 98 views
Discussion

Problems with genvar and nested for loops in verilog-A after updating the Cadence tools

Category: Custom IC Design

By Esmee Tackx
•
started 23 hours ago

0 replies • 44 views
Discussion

Latency to Connect License server

Category: Custom IC Design

By Tarique mohd
•
updated 1 day ago by Saloni Chhabra

3 replies • 133 views
Discussion

Parasitic Extraction Failure in Quantus - Assura

Category: Custom IC Design

By MK202507103018
•
started 2 days ago

0 replies • 50 views
Discussion

Netlisting 'config' view with SPICE source file... CDF parameter m= on symbol is not printed in netlist instance call

Category: Custom IC Design

By JeffBeck
•
updated 6 days ago by JeffBeck

2 replies • 340 views
Discussion

pxf or pac sampled Explanation

Category: Custom IC Design

By Patrick Chang
•
started 6 days ago

0 replies • 166 views
Discussion

calcVal function works during the simulation, but fails after initiating re-evaluation

Category: Custom IC Design

By A1vis
•
updated 6 days ago by A1vis

8 replies • 963 views
Discussion

PSS/Pnoise analysis for divider circuit, input is pulse waveform from vsource with noise profile

Category: Custom IC Design

By Zaara
•
started 7 days ago

0 replies • 142 views
Discussion

Tolerance relaxation when calculating DC operating point - impact on accuracy of SP analysis

Category: Custom IC Design

By Macio
•
updated 7 days ago by Macio

2 replies • 267 views
Discussion

Nested ddt Operator

Category: Custom IC Design

By JF202408126026
•
updated 7 days ago by JF202408126026

2 replies • 186 views
Discussion

using bus pin for inherited connection with AMS

Category: Custom IC Design

By Darrell L
•
started 8 days ago

0 replies • 135 views

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.