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Guidelines for the Custom IC Design Forum
started by on 28 Jul 2011 11:20 PM
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28 Jul 2011 11:20 PM
is it possible to extract the subcircuit names/models and the associated pins from input.scs ?
started by on 19 Feb 2019 12:29 AM
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19 Feb 2019 9:42 AM
recovery
started by on 18 Feb 2019 6:13 PM
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19 Feb 2019 5:07 AM
In layout window up and down arrows are not working for scrolling.. What may be the reason behind it?
started by on 17 Feb 2019 10:43 PM
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19 Feb 2019 5:01 AM
Viva plot colors change on every iteration during real time tuning
started by on 18 Feb 2019 2:48 AM
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18 Feb 2019 5:10 AM
Importing standard cell area into .lib file automatically.
started by on 18 Feb 2019 1:44 AM
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18 Feb 2019 1:44 AM
Cadence schematic showing up all as yellow
started by on 15 Feb 2019 2:07 PM
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17 Feb 2019 9:20 AM
Spectre: TRAN results slightly differ according to which outputs are saved
started by on 13 Feb 2019 12:58 AM
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17 Feb 2019 5:49 AM
ADE XL showing deleted design variables
started by on 14 Feb 2019 7:50 PM
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17 Feb 2019 3:13 AM
Import Verilog
started by on 6 Jan 2011 5:55 PM
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15 Feb 2019 3:55 PM
nested for loop and fwrite statement
started by on 13 Feb 2019 4:12 PM
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15 Feb 2019 9:03 AM
Cannot netlist config view of my testbench
started by on 14 Feb 2019 2:22 PM
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15 Feb 2019 7:01 AM
MDL Autostop Using cross and freq Functions
started by on 13 Feb 2019 2:43 AM
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15 Feb 2019 1:42 AM
Some Calculator Functions in MDL, Using a Variable in MDL
started by on 13 Feb 2019 12:36 AM
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15 Feb 2019 1:42 AM
Warning: ddiAddLibtoOA: Can't access library'Library name" at path "path" in OA 2.2. OA Exception is: Syntax error in .oalib file of the library
started by on 14 Feb 2019 2:49 AM
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14 Feb 2019 10:20 PM

Community Guidelines

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