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Guidelines for the Custom IC Design Forum
started by on 28 Jul 2011 11:20 PM
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28 Jul 2011 11:20 PM
How to copy the outputs setup and the Global variables in the mastero into the ade-XL outputs setup and Global variables respectively
started by on 4 Jul 2020 7:42 AM
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4 Jul 2020 7:42 AM
Unable to change diode parameters when importing the CDL netlist
started by on 1 Jul 2020 1:53 PM
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170
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1 Jul 2020 1:53 PM
Re: WildCard for Spectre Save statement
started by on 30 Jun 2020 1:50 PM
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275
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30 Jun 2020 2:17 PM
Can you set the schematic annotations simulation results directory remotely via ocean?
started by on 26 Jun 2020 8:13 AM
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30 Jun 2020 1:04 PM
ADE-L: how to add include file without using hard-coded paths
started by on 30 Jun 2020 11:07 AM
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30 Jun 2020 12:57 PM
Accounting for physically non equipotential ground pins in LVS
started by on 29 Jun 2020 2:12 AM
4
390
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30 Jun 2020 5:39 AM
GNT library for Virtuoso
started by on 29 Jun 2020 9:16 AM
3
373
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30 Jun 2020 1:56 AM
Disable specific instances or nets within a subcell of a testbench
started by on 29 Jun 2020 4:01 AM
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377
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29 Jun 2020 10:26 AM
alter option
started by on 21 Sep 2018 6:40 AM
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8276
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29 Jun 2020 8:31 AM
Using $table_model in verilogA for finding current for a given temperature
started by on 26 Jun 2020 12:31 PM
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436
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29 Jun 2020 7:23 AM
FreePDK45 usage in Virtuoso
started by on 28 Jun 2020 9:18 AM
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457
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29 Jun 2020 5:15 AM
matching constraint in extracted view simulation
started by on 28 Jun 2020 7:35 PM
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277
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28 Jun 2020 7:35 PM
Can Liberate take encrypted spice netlist
started by on 27 Jun 2020 11:48 AM
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387
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28 Jun 2020 2:50 AM
staircase function
started by on 27 Jun 2020 1:22 AM
1
402
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27 Jun 2020 3:05 AM

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