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Guidelines for the Custom IC Design Forum
started by on 28 Jul 2011 11:20 PM
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28 Jul 2011 11:20 PM
Using variables with spectrumMeas
started by on 7 May 2021 9:47 AM
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7 May 2021 9:47 AM
compare two netlists
started by on 6 May 2021 12:32 AM
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6 May 2021 11:29 AM
Automatically Export Spectre AMS-Output-Data
started by on 3 May 2021 7:52 AM
2
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5 May 2021 6:11 AM
Update global variables from active setup to run plan
started by on 4 May 2021 2:19 AM
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4 May 2021 2:19 AM
ddt() at a certain timestep in Verilog-A
started by on 1 May 2021 9:15 PM
11
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4 May 2021 1:05 AM
Layout XL generating MOS without source contacts.
started by on 30 Apr 2021 6:16 AM
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4 May 2021 12:14 AM
Is there a way to exclude vias when highlighting nets using Net Tracer on Virtuoso?
started by on 3 May 2021 8:27 PM
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3 May 2021 8:27 PM
can analog pad be used as power pad (power is ac sinosuid)
started by on 1 May 2021 4:48 AM
6
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3 May 2021 12:13 PM
HB Analysis on PLL
started by on 19 Apr 2021 7:28 AM
20
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3 May 2021 9:44 AM
How to update schematic without layout
started by on 2 May 2021 7:33 PM
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3 May 2021 2:56 AM
license to run spectre electro-thermal demo
started by on 2 May 2021 6:16 PM
1
116
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3 May 2021 2:47 AM
ADE XL simluation stuck
started by on 30 Apr 2021 11:01 AM
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1 May 2021 9:12 PM
Virtuoso Spice In Device Map property is not honored
started by on 29 Apr 2021 4:52 AM
6
303
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1 May 2021 8:23 AM
Layout offgrid problem
started by on 22 Mar 2021 3:25 PM
4
515
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30 Apr 2021 2:01 AM

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