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Guidelines for the Custom IC Design Forum
started by Andrew Beckett on 28 Jul 2011 11:20 PM

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82713

By Andrew Beckett
28 Jul 2011 11:20 PM

would it be possible to copy a component or block inside a symbol when you descend into a block and copy it out?
started by BaaB on 25 Sep 2020 4:48 AM

3

88

By Andrew Beckett
25 Sep 2020 9:18 AM

Setting PVS for DRC and LVS (tsmcN28)
started by snezana111 on 19 May 2016 4:17 AM

3

40381

By jdimov
25 Sep 2020 6:32 AM

Transient noise analysis - Simulation very slow
started by Tobias Schirmer on 23 Sep 2020 8:55 AM

3

161

By ShawnLogan
24 Sep 2020 11:20 AM

Assura QRC error
started by 24VS on 23 Sep 2020 6:57 PM

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107

By 24VS
23 Sep 2020 6:57 PM

Spectre model aliasing
started by CSCNalu on 23 Sep 2020 1:06 PM

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118

By CSCNalu
23 Sep 2020 1:06 PM

Finfet Stacked CMOS oppoint problem
started by JoshuaXiang on 22 Sep 2020 12:27 AM

1

208

By JoshuaXiang
22 Sep 2020 7:54 PM

Can Liberate take encrypted spice netlist?
started by mailinh on 22 Sep 2020 12:51 AM

1

204

By Andrew Beckett
22 Sep 2020 1:43 AM

How to export top schematic + all sub schematics?
started by ealaiporpi on 22 Sep 2020 1:33 AM

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194

By ealaiporpi
22 Sep 2020 1:33 AM

Plot using waveVsWave function
started by Pedro Cardoso on 21 Sep 2020 4:17 AM

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226

By Pedro Cardoso
21 Sep 2020 4:17 AM

Edit Synchronous clone
started by budman on 18 Sep 2020 12:33 PM

1

328

By Andrew Beckett
19 Sep 2020 12:09 AM

Is there a way to resume a cadence virtuoso that got stuck?
started by venkmanbuster on 18 Sep 2020 4:25 PM

1

348

By Andrew Beckett
19 Sep 2020 12:07 AM

What's the bindkey command for ascend to top level on Cadence?
started by venkmanbuster on 2 Aug 2020 5:15 PM

3

613

By venkmanbuster
18 Sep 2020 4:26 PM

ModGen tool is violating the DRC rules
started by Senan on 18 Sep 2020 6:25 AM

1

347

By Andrew Beckett
18 Sep 2020 8:48 AM

ADE XL showing deleted design variables
started by wgtkan on 14 Feb 2019 7:50 PM

7

5748

By Andrew Beckett
18 Sep 2020 3:10 AM

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