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  • Thierry Berdah
    Why Is the Evolving HBM3 Such a Revolutionary Technology and How Can You Be Ready for It?
    By Thierry Berdah | 14 May 2020
    Since 2013, we have seen the HBM specifications being released by JEDEC and companies announcing in the same month HBM products just like magic. How can these companies have a silicon-proven product altogether with newly announced official specifications? What is the secret process they use in order to be constantly first-in-market with these new technologies? And more important, what can YOU do in order to also be such...
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    Tags:
    Verification IP | Memory | VIP | JEDEC | HBM | storage | Design IP and Verification IP | verification
  • William Chen
    PCI-SIG DevCon 2019 APAC Tour: All Around Latest Spec Updates and Solution Offering
    By William Chen | 29 Oct 2019
    PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus is predominantly around the latest updates for PCIe Gen 5 which its version 1.0 specification was just released this year in May. A series of presentations provided by PCI-SIG on the day 1 with comprehensive information covering all aspects of Gen 5 specification, including protocol, logical, electrical, compliance updates. On the day 2 ...
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    Tags:
    PCI Developers Conference | Design IP | PCIe Gen4 | PCIe Gen3 | PCIe PHY | PCIe Gen5 | PCI Express | PCI-SIG
  • William Chen
    Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product
    By William Chen | 17 Oct 2019
    The PCI-SIG finalized the PCIe 4.0 specification with doubling the data to 16GT/s from 8GT/s in PCIe 3.0 in 2017. Products implementing this technology have begun to hit the market in 2019. Earlier this year, AMD announced it X570 chipset would support the PCIe 4.0 interface and Phison also introduced the world’s first PCIe 4.0 SSD. With the increasing companies are working on PCIe 4.0 related product development, Cadence...
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    Tags:
    PCIe controller | Design IP | IP | PCIe Gen4 | PHY | IP design | PCIe | semiconductor IP | SerDes | PCIe PHY | PCI Express
  • William Chen
    PCIe 3.0 Still Shines While PCIe Keeps Evolving
    By William Chen | 15 Oct 2019
    PCIe has been widely adopted in the electronics industry since its first debut in 2003 (PCIe 1.0 standard release) for wide breach of applications, from Data Center Server, Networking, to Mobile, AI/ML, Automotive, IoT, and many others…. It’s a versatile, high-performance, robust, mature interconnect standard with full “backward compatibility” (e.g., a PCIe 3.0 device can still function well in a PCIe 4.0 system) which...
    0 Comments
    Tags:
    USB 3.0 | Design IP | IP | USB Type-C | DisplayPort | PCIe | PCIe Gen3 | SerDes | USB 3.1
  • TomWong
    Is the Role of Test Chips Changing at Advanced Foundry Nodes?
    By TomWong | 15 Jul 2019
    Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long been making test chips to...
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    Tags:
    Design IP | IP | cadence | PCIe Gen4 | IP integration | ip cores | Ethernet | semiconductor IP | PCI Express
  • DimitryP
    AMBA Adaptive Traffic Profiles: Addressing The Challenge
    By DimitryP | 9 Jul 2019
    Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and autonomous driving. With increased number of SoC components, such as CPUs, GPUs, accelerators and I/O devices, comes increased demand to correctly model interoperability of various components. Traditional simulation of complex...
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    Tags:
    Adaptive Traffic Profiles | Performance modeling | AMBA | ATP
  • TomWong
    SemiEngineering Article: Why IP Quality Is So Difficult to Determine
    By TomWong | 7 Jun 2019
    Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends upon how and where it is used and in part, because even the best IP may work better in one system than another—even in chips developed by the same vendor. So, how do you measure IP quality and why it is so complicated? The answer depends on who is asking. Most of the time, the definition of IP quality depends on...
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    Tags:
    IP | cadence | IP blocks | Automotive Ethernet | ip cores | Tensilica | semiconductor IP | Design IP and Verification IP
  • TomWong
    Designing for the Future - Managing the Impact of Moore's Law
    By TomWong | 15 May 2019
    With Moore’s Law, the industry assumes that when you go from one geometry to the next finer node, you will have performance gains. All this is automatic. Chip designers have tried to leverage improvements in process technology to get performance improvements for many years now. Let’s examine whether or not this assumption is still valid. When we were at more mature technologies, such as 90nm to 65nm, there may have...
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    Tags:
    Design IP | IP | LPDDR | PCIe Gen4 | MIPI | USB | SerDes
  • PaulaJones
    NXP Introduces Tensilica HiFi 4 DSP-based Platforms to Secure IoT Edge Devices
    By PaulaJones | 10 Oct 2018
    Trust. Privacy. Confidentiality. These are three important concerns for designers of IoT edge devices. Today NXP announced that they are addressing these concerns with two new platforms that feature secure execution environment (SEE) to give developers access to “unprecedented” security capabilities. These platforms provide a multi-layered, hardware-enabled protection scheme to secure IoT edge devices and cloud-to...
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    Tags:
    IP | IoT | HiFi | ip cores | Tensilica | semiconductor IP | Internet of Things
  • PaulaJones
    Cadence Tensilica Fusion F1 DSP Stars in NB IoT Applications
    By PaulaJones | 2 Jul 2018
    Did you make it to MWC Shanghai? I didn’t, but I read about what was hot – narrowband (NB) IoT. Three of Cadence’s customers had Tensilica Fusion F1 DSP demos on the show floor. Xinyi Information Technology, a China-based company, showed off the first single-core modem that integrates a CMOS power amplifier with the modem. Their Marconi X1 modem features an NB-IoT protocol stack from Huachang Technology, who was able...
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    Tags:
    DSP | IoT | Fusion | ip cores | Tensilica | nb-iot
  • TomWong
    Chip Dis-integration
    By TomWong | 27 Jun 2018
    I was asked the following question recently. No longer are we seeing increasing amounts of functionality being crammed into chips, except under very special circumstances. Chips today are trending towards the leaner side. Is this only when power is a primary concern? Does this apply to all technology nodes or only to larger ones? What about pins – I/O has often been the limiter. What impact will this have on IP? Will...
    0 Comments
    Tags:
    chiplets | IoT | Design IP and Verification IP | moore's law | 2.5D interposer
  • PaulaJones
    Why Software-Based GPS Is Great for Location-Based IoT Applications
    By PaulaJones | 27 Feb 2018
    At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo of a software-based GPS receiver from Galileo Satellite Navigation running off a Cadence Tensilica Fusion F1 DSP. It’s a very impressive demo—come by...
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  • tomhackett
    Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP
    By tomhackett | 23 Feb 2018
    What is a software GPS, what does it have to do with Tensilica DSP IP, and why would anyone care? To answer that, let's start with a quiz from the transportation industry. How many shipping containers are currently in transit around the world? It turns out that no one knows for sure, but the best guess is that there are about 20 million containers in service today. And it's a safe bet that those containers are carrying...
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    Tags:
    Galileo | GPS | IoT | Tensilica DSPs
  • DimitryP
    New AMBA 5 ACE/AXI Specification: More About Atomic Transactions
    By DimitryP | 22 Feb 2018
    As discussed in the previous installment of this blog, a new class of atomic transactions was introduced in the AMBA® 5 ACE/AXI specification to make operations at the remote locations more streamlined and efficient. We have considered an example of AtomicStore transaction with ADD operation and discussed why it was more efficient than relying on the older semaphore-like exclusive operations. In this installment of the...
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    Tags:
    amba5 | ACE5 | AXI5 | Atomic Transactions
  • PaulaJones
    See You in Barcelona at MWC!
    By PaulaJones | 12 Feb 2018
    I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never fails to amaze me. This year’s theme is “Creating a Better Future” and I can’t think of a better theme for Cadence – our Tensili...
    0 Comments
    Tags:
    DSP | IP | Mobile World Congress | ip cores | Tensilica | vision | imaging
  • tomhackett
    What I Learned About System Design Enablement at DesignCon
    By tomhackett | 9 Feb 2018
    While attending the recent DesignCon show for the first time, I was struck by the many displays of cables, connectors, boards, and various kinds of test equipment (you can read about the impact this had on me in my previous post, A Walk Through DesignCon Turns Into a Long Journey ). There was so much hardware, in fact, that I felt like I was walking through a giant Fry’s store. The impression was so strong that my first...
    0 Comments
    Tags:
    IP | IP integration | SDE | Sigrity | system design enablement
  • tomhackett
    A Walk Through DesignCon Turns Into a Long Journey
    By tomhackett | 9 Feb 2018
    Have you ever attended the DesignCon show? I attended the recent event for the first time and was surprised by what I saw: tons of high-bandwidth coax cables, circuit boards, connectors, and other hardware—all harnessed to very expensive scopes and channel analyzers displaying perfect eye diagrams. This was definitely a show for hardware engineers. Walking around the show floor brought on an unexpected feeling...
    0 Comments
    Tags:
    IP | IP integration | SDE | noise | Sigrity
  • DimitryP
    New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions
    By DimitryP | 1 Feb 2018
    The recent update of the AMBA® 5 ACE/AXI specification introduces a number of significant performance improvements which help to align the protocol to the more recent AMBA® 5 CHI (Coherent Hub Interface) specification. One of the most prominent features is introduction of atomic transactions. Before we take a close look at this new class of transactions, let’s look back in time. Previous generations of AMBA ACE/AXI...
    0 Comments
    Tags:
    amba5 | ACE5 | AXI5 | AMBA
  • PaulaJones
    You Won't Believe Your Ears When Listening to Your Laptop
    By PaulaJones | 31 Jan 2018
    I wouldn't believe it if I hadn't heard it myself on a laptop in the Cadence booth at the Consumer Electronics Show ( CES) this year. Through a great innovation by our partner Dolby, you can now get surround sound on your laptop! You’ve probably been in a movie theater with Dolby’s latest innovation— Dolby Atmos . And maybe you’ve purchased a television in the last year with Dolby Atmos (it was a huge sensation at...
    0 Comments
    Tags:
    CES | audio | HiFi | Tensilica
  • PaulaJones
    Book Your CES Meetings Now!
    By PaulaJones | 4 Dec 2017
    Want to see the exciting technology that is behind some of the biggest innovations at CES? Book a meeting now to visit the Cadence invitation-only suites at CES 2018, January 9-12, South Hall 2, Suite MP2577 (same location as last year). See Tensilic...
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  • Jacek Duda
    USB 3.2—The USB Type-C Connector Finally Met its Match
    By Jacek Duda | 19 Sep 2017
    It’s only a week before the first event of USB Developer Days , a series of meetings for USB developers, where the USB 3.2 specification will be formally announced. Much like with any recent smartphone announcement, we know pretty much everything about the new standard before it’s formally announced. We know that the big news is the 20Gbps support, twice the performance of the previous (USB 3.1 Gen 2) standard, which...
    0 Comments
    Tags:
    USB 3.0 | USB Type-C | DisplayPort | USB | USB 3.2 | power delivery | USB 3.1
  • PaulaJones
    Cadence IP Is Great for Automotive
    By PaulaJones | 12 Sep 2017
    If you’re designing chips for in-vehicle infotainment, in-cabin electronics, vision systems, digital noise reduction, and advanced driver assistance systems (ADAS), look at Cadence for the key IP to speed your design effort. We just announced that we have collaborated with a major foundry to produce an IP portfolio that’s ASIL-B ready and ASIL-C/D capable. See the press release for full details. Cadence IP is area...
    0 Comments
    Tags:
    USB 3.0 | Design IP | DDR4 | LPDDR4 | PCI Express 3.0 | LPDDR | IP blocks | PCIe Gen4 | MIPI | DisplayPort | Automotive Ethernet | USB | memory IP | Ethernet | PCIe | 16nm | PCIe Gen3 | imaging | Ethernet PHYs | PCI
  • Sachin Dhingra
    What’s New With Cadence PCI Express IP? Almost Everything!
    By Sachin Dhingra | 22 Aug 2017
    PCI-SIG Developer’s Conference 2017 was held in Santa Clara, California in June this year where several hundred customers from more than a hundred unique companies visited the conference. The next-generation PCI Express (PCIe) 5.0 specification was announced with plans for ratification in 2019. The announcement had a supporting quote by Cadence confirming our long-term commitment to developing products for PCIe interface...
    0 Comments
    Tags:
    IP | TSMC | Gen4 | PCIe | 16nm | PCI Express 4.0 | 7nm | PCI-SIG
  • It's a Visual World
    By MeeraC | 22 Aug 2017
    Here’s an experiment to try: in a quiet (but crowded) Auditorium, drop a stack of plates. Hypothesis: At the first splinters of the crash, all eyes will jerk to the source of the sound. You probably won’t get many people listening harder to find out what happened. Yes, our hearing can give us a lot of information, too—it can indicate direction, distance, magnitude, and even give some ideas about what happened ...
    0 Comments
    Tags:
    controller IP | Design IP | IP | IP blocks | Embedded Vision Summit | vision processing | Jitendra Malik | IP design | Tensilica | vision | future of IP | Design IP and Verification IP | imaging | image processing
  • PaulaJones
    Happy Birthday Tensilica
    By PaulaJones | 31 Jul 2017
    Yes, it’s Tensilica’s birthday! Twenty years ago today, on July 31, 1997, Tensilica was officially incorporated by Chris Rowen, who I knew from our Synopsys days when he was VP of the Design Reuse Business Unit. I started working with Tensilica (as a PR consultant) when there were eight people in the office next to the Duke of Edinburgh pub on Wolfe road in Cupertino. I became a Tensilica employee in 2002, and worked...
    0 Comments
    Tags:
    DSP | Chris Rowen | HiFi | Tensilica | vision
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