SoC Integration - Cadence Blogs

FMEDA-driven SoC Design of Safety-Critical Semiconductors

Written by Francesco Lertora and Robert Schweiger 1.1 Introduction The growing…

Robbie 18 Jan 2023 • 8 min read

Safety Solution , Genus , functional safety , Midas Safety Platform , Xcelium Safety , Jasper FSV , Verisium Manager Safety , USF , Automotive Option , Safety Analysis , Innovus , FMEDA , ISO 26262 , Virtuoso Assembler , Unified Safety Format , Safety Verification , Safety Compliance , Legato Reliability , Safety-aware Implementation

Building Robust PCI Express IP Solutions: Compliance and Beyond

Discover PCIe Going from draft specification to being listed as compliant on the…

Arif Khan 15 Aug 2022 • 3 min read

featured , PCIe , PCI Express

AI in Healthcare

Artificial Intelligence and edge computing are revolutionizing the healthcare industry…

Vinod Khera 27 Jun 2022 • 4 min read

artificial intelligence , Edge Computing , healthcare , AI

TWS Earbud Design: Scaling up

We now look to scale the architecture from Good-enough earbuds, to Better (mid-tier…

The Prakashian 4 Apr 2022 • 9 min read

Tensilica DSPs , Tensilica

TWS Earbud Design Is About Scaling

It is important that OEMs and SoC providers of TWS earbuds prepare to offer the quality…

The Prakashian 4 Apr 2022 • 5 min read

featured , Tensilica

Leveraging Vision for Depth Perception in Autonomous Driving

The automotive industry is inching towards enhancing the driver’s experience and…

Vinod Khera 10 Mar 2022 • 6 min read

autonomous driving , depth , Tensilica , iso26262 , ADAS , fusa

High-Speed 112G Design and COM Dependencies

The design impairments such as SoC packaging, package-to-board impedance mismatch…

Vinod Khera 7 Feb 2022 • 5 min read

high-speed , 112g , SerDes , SerDes IP , COM Dependencies , Log-Reach

Improving Performance and Throughput While Implementing FFT Using Tensilica ConnXB20…

Real-time FFT performance in Radar, Lidar, and ADAS applications is limited by…

Vinod Khera 12 Jan 2022 • 6 min read

DSP , cadence , tie , semiconductor IP , DIT , Tensilica IP , FFT

PCIe for Automotive - DesignCon/DriveWorld 2021

DesignCon 2021, Drive World Conference, and Embedded Systems Conference are a joint…

TomWong 20 Aug 2021 • 3 min read

CXL , Design IP , IP , featured , PCIe Gen4 , ip cores , PCI , PCIe PHY

Introducing Cadence IP for PCIe 6.0

Since its inception, PCI Express® (PCIe®) has proliferated quickly to become ubiquitous…

tonychen6636 24 May 2021 • 3 min read

controller IP , CXL , Design IP , IP , PHY , PCIe , semiconductor IP , SerDes , PCIe 6.0 , PCI Express

First Look: Cadence Subsystem SoC for PCIe 5.0

If a picture is worth a thousand words, a video tells you the entire story. Cadence…

Arif Khan 13 Apr 2021 • 1 min read

controller IP , CXL , PCI Express 5.0 , Design IP , IP , PHY , Gen5 , PCIe , semiconductor IP , Design and Verification IP , SerDes , Compute Express Link , SerDes IP , PCI Express

Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0

Cadence was the first IP provider to bring controllers for PCI Express (PCIe) 3…

Arif Khan 12 Apr 2021 • 2 min read

controller IP , CXL , PCI Express 5.0 , Design IP , IP , PHY , Gen5 , PCIe , semiconductor IP , Design IP and Verification IP , SerDes , Compute Express Link , SerDes IP , PCI , PCI Express

PCI-SIG DevCon 2019 APAC Tour: All Around Latest Spec Updates and Solution Offer…

PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus…

William Chen 29 Oct 2019 • 2 min read

PCI Developers Conference , Design IP , PCIe Gen4 , PCIe Gen3 , PCIe PHY , PCIe Gen5 , PCI Express , PCI-SIG

Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product

The PCI-SIG finalized the PCIe 4.0 specification with doubling the data to 16GT…

William Chen 17 Oct 2019 • 2 min read

PCIe controller , Design IP , IP , PCIe Gen4 , PHY , IP design , PCIe , semiconductor IP , SerDes , PCIe PHY , PCI Express

PCIe 3.0 Still Shines While PCIe Keeps Evolving

PCIe has been widely adopted in the electronics industry since its first debut in…

William Chen 15 Oct 2019 • 2 min read

USB 3.0 , Design IP , IP , USB Type-C , DisplayPort , PCIe , PCIe Gen3 , SerDes , USB 3.1

Is the Role of Test Chips Changing at Advanced Foundry Nodes?

Test chips are becoming more widespread and more complex at advanced process nodes…

TomWong 15 Jul 2019 • 3 min read

Design IP , IP , cadence , PCIe Gen4 , IP integration , ip cores , Ethernet , semiconductor IP , PCI Express

SemiEngineering Article: Why IP Quality Is So Difficult to Determine

Differentiating good IP from mediocre or bad IP is getting more difficult, in part…

TomWong 7 Jun 2019 • 3 min read

IP , cadence , IP blocks , Automotive Ethernet , ip cores , Tensilica , semiconductor IP , Design IP and Verification IP

Designing for the Future - Managing the Impact of Moore's Law

With Moore’s Law, the industry assumes that when you go from one geometry to the…

TomWong 15 May 2019 • 3 min read

Design IP , IP , LPDDR , PCIe Gen4 , MIPI , USB , SerDes

NXP Introduces Tensilica HiFi 4 DSP-based Platforms to Secure IoT Edge Devices

Trust. Privacy. Confidentiality. These are three important concerns for designers…

PaulaJones 10 Oct 2018 • 1 min read

IP , IoT , HiFi , ip cores , Tensilica , semiconductor IP , Internet of Things

Cadence Tensilica Fusion F1 DSP Stars in NB IoT Applications

Did you make it to MWC Shanghai? I didn’t, but I read about what was hot – narrowband…

PaulaJones 2 Jul 2018 • 1 min read

DSP , IoT , Fusion , ip cores , Tensilica , nb-iot

Chip Dis-integration

I was asked the following question recently. No longer are we seeing increasing…

TomWong 27 Jun 2018 • 5 min read

chiplets , IoT , Design IP and Verification IP , moore's law , 2.5D interposer

Why Software-Based GPS Is Great for Location-Based IoT Applications

At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo…

PaulaJones 27 Feb 2018 • 1 min read

Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would…

tomhackett 23 Feb 2018 • 4 min read

Galileo , GPS , IoT , Tensilica DSPs

See You in Barcelona at MWC!

I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never…

PaulaJones 12 Feb 2018 • 1 min read

DSP , IP , Mobile World Congress , ip cores , Tensilica , vision , imaging

What I Learned About System Design Enablement at DesignCon

While attending the recent DesignCon show for the first time, I was struck by the…

tomhackett 9 Feb 2018 • 2 min read

IP , IP integration , SDE , Sigrity , system design enablement

A Walk Through DesignCon Turns Into a Long Journey

Have you ever attended the DesignCon show? I attended the recent event for the first…

tomhackett 9 Feb 2018 • 2 min read

IP , IP integration , SDE , noise , Sigrity

You Won't Believe Your Ears When Listening to Your Laptop

I wouldn't believe it if I hadn't heard it myself on a laptop in the Cadence booth…

PaulaJones 31 Jan 2018 • 2 min read

CES , audio , HiFi , Tensilica

Book Your CES Meetings Now!

Want to see the exciting technology that is behind some of the biggest innovations…

PaulaJones 4 Dec 2017 • 1 min read

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