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Tensilica and Design IP
  • Arif Khan
    Building Robust PCI Express IP Solutions: Compliance and Beyond
    By Arif Khan | 15 Aug 2022
    Discover PCIe Going from draft specification to being listed as compliant on the integrators list by PCI-SIG is a multiple-year journey. The preliminary PCIe® 5.0 specification was announced in June 2017, with the final specification released in May 2019 and the first official compliance workshop conducted in April 2022. This represents the complexity of the products being built and the ecosystem required to support...
    0 Comments
    Tags:
    PCIe | PCI Express
  • Vinod Khera
    AI in Healthcare
    By Vinod Khera | 27 Jun 2022
    Artificial Intelligence and edge computing are revolutionizing the healthcare industry. The recent progress in these technologies is helping medical experts diagnose accurately and quickly.
    0 Comments
    Tags:
    artificial intelligence | Edge Computing | healthcare | AI
  • The Prakashian
    TWS Earbud Design: Scaling up
    By The Prakashian | 4 Apr 2022
    We now look to scale the architecture from Good-enough earbuds, to Better (mid-tier) and Best (high-end) models. While adding features and improving user experience, we hope to preserve the software investment made by OEM and/or SoC vendors. This is essential for fast time-to-market, as we reach to grab a larger portion of the available market TAM.
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    Tags:
    Tensilica DSPs | Tensilica
  • The Prakashian
    TWS Earbud Design Is About Scaling
    By The Prakashian | 4 Apr 2022
    It is important that OEMs and SoC providers of TWS earbuds prepare to offer the quality and features the market expects of next generation products. Here, we explore the architecture of the signal path and the approach to scaling it across different product tiers.
    0 Comments
    Tags:
    Tensilica
  • Vinod Khera
    Leveraging Vision for Depth Perception in Autonomous Driving
    By Vinod Khera | 10 Mar 2022
    The automotive industry is inching towards enhancing the driver’s experience and overall safety. We have seen a plethora of technological innovations such as ADAS, tire pressure monitoring, automated emergency braking, IOT etc. that have improved vehicle performance, efficiency, reliability, and safety. Autonomous driving is leading to major disruptions in the automotive industry. Light used Tensilica V7 for depth perception...
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    Tags:
    autonomous driving | depth | Tensilica | iso26262 | ADAS | fusa
  • Vinod Khera
    High-Speed 112G Design and COM Dependencies
    By Vinod Khera | 7 Feb 2022
    The design impairments such as SoC packaging, package-to-board impedance mismatch, and crosstalk due to front panel and backplane connector, as well as noise coupling could have a significant impact on the bit error rate (BER) in a production system. mentioned in Such design impairments These impairments have a much bigger impact as we move towards 112G data rate because of smaller UI and lower SNR. By prescribing the...
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    Tags:
    high-speed | 112g | SerDes | SerDes IP | COM Dependencies | Log-Reach
  • Vinod Khera
    Improving Performance and Throughput While Implementing FFT Using Tensilica ConnXB20 DSP with TIE
    By Vinod Khera | 12 Jan 2022
    Real-time FFT performance in Radar, Lidar, and ADAS applications is limited by data bandwidth, data reordering and shuffling of data, and increases in complexity as the size of FFT increases. Using a parallel FFT architecture scheme eliminates such limitations and results in better resource utilization and up to 3126 X speed up.
    0 Comments
    Tags:
    DSP | cadence | tie | semiconductor IP | DIT | Tensilica IP | FFT
  • TomWong
    PCIe for Automotive - DesignCon/DriveWorld 2021
    By TomWong | 20 Aug 2021
    DesignCon 2021, Drive World Conference, and Embedded Systems Conference are a joint event this year. Cadence had an opportunity to present at a session on behalf of PCI-SIG. The topic of the presentation is "PCI Express Technology: Accelerating Automotive Connectivity, from Infotainment to ADAS." I covered the portion on automotive trends and highlighted the various new automotive applications that are driving the transition...
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    Tags:
    CXL | Design IP | IP | PCIe Gen4 | ip cores | PCI | PCIe PHY
  • tonychen6636
    Introducing Cadence IP for PCIe 6.0
    By tonychen6636 | 24 May 2021
    Since its inception, PCI Express® (PCIe®) has proliferated quickly to become ubiquitous in the modern digital world. Today, PCIe is an indispensable technology found in high-performance computing, AI/ML accelerators, network adapters, and solid-state storage, to name a few. In addition, recent advances in speed and latency of PCIe have allowed it to gain wider adoption within the memory hierarchy as well (e.g., persistent...
    0 Comments
    Tags:
    controller IP | CXL | Design IP | IP | PHY | PCIe | semiconductor IP | SerDes | PCIe 6.0 | PCI Express
  • Arif Khan
    First Look: Cadence Subsystem SoC for PCIe 5.0
    By Arif Khan | 13 Apr 2021
    If a picture is worth a thousand words, a video tells you the entire story. Cadence's subsystem SoC silicon for PCI Express (PCIe) 5.0 demo video shows you how we put together the latest technology in TSMC's advanced FinFET technology to bring to market a compelling, low-power solution and tested it with the latest industry test solutions available. https://youtu.be/Mgy5Z-sKs6E The subsystem contains Cadence's...
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    Tags:
    controller IP | CXL | PCI Express 5.0 | Design IP | IP | PHY | Gen5 | PCIe | semiconductor IP | Design and Verification IP | SerDes | Compute Express Link | SerDes IP | PCI Express
  • Arif Khan
    Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0
    By Arif Khan | 12 Apr 2021
    Cadence was the first IP provider to bring controllers for PCI Express (PCIe) 3.0 to the market and the lowest power 3.0 PHY at introduction. We're proud to continue the trend with our solution for PCIe 5.0 that continues to blaze the trail with new benchmarks for power, performance, and area. Figure 1: I/O Bandwidth doubling every three years and PCI Specification Updates The PCIe standard has been around for...
    0 Comments
    Tags:
    controller IP | CXL | PCI Express 5.0 | Design IP | IP | PHY | Gen5 | PCIe | semiconductor IP | Design IP and Verification IP | SerDes | Compute Express Link | SerDes IP | PCI | PCI Express
  • William Chen
    PCI-SIG DevCon 2019 APAC Tour: All Around Latest Spec Updates and Solution Offering
    By William Chen | 29 Oct 2019
    PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus is predominantly around the latest updates for PCIe Gen 5 which its version 1.0 specification was just released this year in May. A series of presentations provided by PCI-SIG on the day 1 with comprehensive information covering all aspects of Gen 5 specification, including protocol, logical, electrical, compliance updates. On the day 2 ...
    0 Comments
    Tags:
    PCI Developers Conference | Design IP | PCIe Gen4 | PCIe Gen3 | PCIe PHY | PCIe Gen5 | PCI Express | PCI-SIG
  • William Chen
    Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product
    By William Chen | 17 Oct 2019
    The PCI-SIG finalized the PCIe 4.0 specification with doubling the data to 16GT/s from 8GT/s in PCIe 3.0 in 2017. Products implementing this technology have begun to hit the market in 2019. Earlier this year, AMD announced it X570 chipset would support the PCIe 4.0 interface and Phison also introduced the world’s first PCIe 4.0 SSD. With the increasing companies are working on PCIe 4.0 related product development, Cadence...
    0 Comments
    Tags:
    PCIe controller | Design IP | IP | PCIe Gen4 | PHY | IP design | PCIe | semiconductor IP | SerDes | PCIe PHY | PCI Express
  • William Chen
    PCIe 3.0 Still Shines While PCIe Keeps Evolving
    By William Chen | 15 Oct 2019
    PCIe has been widely adopted in the electronics industry since its first debut in 2003 (PCIe 1.0 standard release) for wide breach of applications, from Data Center Server, Networking, to Mobile, AI/ML, Automotive, IoT, and many others…. It’s a versatile, high-performance, robust, mature interconnect standard with full “backward compatibility” (e.g., a PCIe 3.0 device can still function well in a PCIe 4.0 system) which...
    0 Comments
    Tags:
    USB 3.0 | Design IP | IP | USB Type-C | DisplayPort | PCIe | PCIe Gen3 | SerDes | USB 3.1
  • TomWong
    Is the Role of Test Chips Changing at Advanced Foundry Nodes?
    By TomWong | 15 Jul 2019
    Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long been making test chips to...
    0 Comments
    Tags:
    Design IP | IP | cadence | PCIe Gen4 | IP integration | ip cores | Ethernet | semiconductor IP | PCI Express
  • TomWong
    SemiEngineering Article: Why IP Quality Is So Difficult to Determine
    By TomWong | 7 Jun 2019
    Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends upon how and where it is used and in part, because even the best IP may work better in one system than another—even in chips developed by the same vendor. So, how do you measure IP quality and why it is so complicated? The answer depends on who is asking. Most of the time, the definition of IP quality depends on...
    0 Comments
    Tags:
    IP | cadence | IP blocks | Automotive Ethernet | ip cores | Tensilica | semiconductor IP | Design IP and Verification IP
  • TomWong
    Designing for the Future - Managing the Impact of Moore's Law
    By TomWong | 15 May 2019
    With Moore’s Law, the industry assumes that when you go from one geometry to the next finer node, you will have performance gains. All this is automatic. Chip designers have tried to leverage improvements in process technology to get performance improvements for many years now. Let’s examine whether or not this assumption is still valid. When we were at more mature technologies, such as 90nm to 65nm, there may have...
    0 Comments
    Tags:
    Design IP | IP | LPDDR | PCIe Gen4 | MIPI | USB | SerDes
  • PaulaJones
    NXP Introduces Tensilica HiFi 4 DSP-based Platforms to Secure IoT Edge Devices
    By PaulaJones | 10 Oct 2018
    Trust. Privacy. Confidentiality. These are three important concerns for designers of IoT edge devices. Today NXP announced that they are addressing these concerns with two new platforms that feature secure execution environment (SEE) to give developers access to “unprecedented” security capabilities. These platforms provide a multi-layered, hardware-enabled protection scheme to secure IoT edge devices and cloud-to...
    0 Comments
    Tags:
    IP | IoT | HiFi | ip cores | Tensilica | semiconductor IP | Internet of Things
  • PaulaJones
    Cadence Tensilica Fusion F1 DSP Stars in NB IoT Applications
    By PaulaJones | 2 Jul 2018
    Did you make it to MWC Shanghai? I didn’t, but I read about what was hot – narrowband (NB) IoT. Three of Cadence’s customers had Tensilica Fusion F1 DSP demos on the show floor. Xinyi Information Technology, a China-based company, showed off the first single-core modem that integrates a CMOS power amplifier with the modem. Their Marconi X1 modem features an NB-IoT protocol stack from Huachang Technology, who was able...
    0 Comments
    Tags:
    DSP | IoT | Fusion | ip cores | Tensilica | nb-iot
  • TomWong
    Chip Dis-integration
    By TomWong | 27 Jun 2018
    I was asked the following question recently. No longer are we seeing increasing amounts of functionality being crammed into chips, except under very special circumstances. Chips today are trending towards the leaner side. Is this only when power is a primary concern? Does this apply to all technology nodes or only to larger ones? What about pins – I/O has often been the limiter. What impact will this have on IP? Will...
    0 Comments
    Tags:
    chiplets | IoT | Design IP and Verification IP | moore's law | 2.5D interposer
  • PaulaJones
    Why Software-Based GPS Is Great for Location-Based IoT Applications
    By PaulaJones | 27 Feb 2018
    At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo of a software-based GPS receiver from Galileo Satellite Navigation running off a Cadence Tensilica Fusion F1 DSP. It’s a very impressive demo—come by...
    0 Comments
  • tomhackett
    Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP
    By tomhackett | 23 Feb 2018
    What is a software GPS, what does it have to do with Tensilica DSP IP, and why would anyone care? To answer that, let's start with a quiz from the transportation industry. How many shipping containers are currently in transit around the world? It turns out that no one knows for sure, but the best guess is that there are about 20 million containers in service today. And it's a safe bet that those containers are carrying...
    0 Comments
    Tags:
    Galileo | GPS | IoT | Tensilica DSPs
  • PaulaJones
    See You in Barcelona at MWC!
    By PaulaJones | 12 Feb 2018
    I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never fails to amaze me. This year’s theme is “Creating a Better Future” and I can’t think of a better theme for Cadence – our Tensili...
    0 Comments
    Tags:
    DSP | IP | Mobile World Congress | ip cores | Tensilica | vision | imaging
  • tomhackett
    What I Learned About System Design Enablement at DesignCon
    By tomhackett | 9 Feb 2018
    While attending the recent DesignCon show for the first time, I was struck by the many displays of cables, connectors, boards, and various kinds of test equipment (you can read about the impact this had on me in my previous post, A Walk Through DesignCon Turns Into a Long Journey ). There was so much hardware, in fact, that I felt like I was walking through a giant Fry’s store. The impression was so strong that my first...
    0 Comments
    Tags:
    IP | IP integration | SDE | Sigrity | system design enablement
  • tomhackett
    A Walk Through DesignCon Turns Into a Long Journey
    By tomhackett | 9 Feb 2018
    Have you ever attended the DesignCon show? I attended the recent event for the first time and was surprised by what I saw: tons of high-bandwidth coax cables, circuit boards, connectors, and other hardware—all harnessed to very expensive scopes and channel analyzers displaying perfect eye diagrams. This was definitely a show for hardware engineers. Walking around the show floor brought on an unexpected feeling...
    0 Comments
    Tags:
    IP | IP integration | SDE | noise | Sigrity
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