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New AMBA 5 ACE/AXI Specification and Its Support in Cadence ACE/AXI VIP

By Dimitry Pavlovsky | 3 Apr 2018

As discussed in the previous installments of the blog, the recent update of the AMBA ® 5 ACE/AXI specification introduced several performance improvement features which align the AMBA5 ACE/AXI protocol with AMBA 5 CHI (Coherent Hub Interface) specification. Among them is the new class of atomic transactions, discussed in-depth previously. Another new transaction class includes the new cache stash transactions which...

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amba5 | Verification IP | ACE VIP | AXI VIP | AMBA
NVMe Express 1.3: Addressing the Storage Needs of the Data Revolution from Enterprise to Client

By Lana Chan | 2 Apr 2018

The amount of data we are generating and consuming has exploded in recent years. Social media, applications, multimedia streaming, 24-hour connectivity has us talking about Zettabytes of data in the data center that folks want to not only store, but analyze and access rapidly. SSDs were great to address mechanical inefficiencies of HDD. However, the constraints of the SCSI protocol still meant that you can only address...

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Verification IP | NVM Express | NVMe | IoT | VIP | cloud | big data | storage | PCIe | PCI Express | data centers
Why Software-Based GPS Is Great for Location-Based IoT Applications

By PaulaJones | 27 Feb 2018

At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo of a software-based GPS receiver from Galileo Satellite Navigation running off a Cadence Tensilica Fusion F1 DSP. It’s a very impressive demo—come by...

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Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

By Thomas Hackett | 23 Feb 2018

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would anyone care? To answer that, let's start with a quiz from the transportation industry. How many shipping containers are currently in transit around the world? It turns out that no one knows for sure, but the best guess is that there are about 20 million containers in service today. And it's a safe bet that those containers are carrying...

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Galileo | GPS | IoT | Tensilica DSPs
New AMBA 5 ACE/AXI Specification: More About Atomic Transactions

By Dimitry Pavlovsky | 22 Feb 2018

As discussed in the previous installment of this blog, a new class of atomic transactions was introduced in the AMBA® 5 ACE/AXI specification to make operations at the remote locations more streamlined and efficient. We have considered an example of AtomicStore transaction with ADD operation and discussed why it was more efficient than relying on the older semaphore-like exclusive operations. In this installment of the...

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amba5 | ACE5 | AXI5 | Atomic Transactions
See You in Barcelona at MWC!

By PaulaJones | 12 Feb 2018

I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never fails to amaze me. This year’s theme is “Creating a Better Future” and I can’t think of a better theme for Cadence – our Tensili...

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DSP | IP | Mobile World Congress | ip cores | Tensilica | vision | imaging
What I Learned About System Design Enablement at DesignCon

By Thomas Hackett | 9 Feb 2018

While attending the recent DesignCon show for the first time, I was struck by the many displays of cables, connectors, boards, and various kinds of test equipment (you can read about the impact this had on me in my previous post, A Walk Through DesignCon Turns Into a Long Journey ). There was so much hardware, in fact, that I felt like I was walking through a giant Fry’s store. The impression was so strong that my first...

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IP | IP integration | SDE | Sigrity | system design enablement
A Walk Through DesignCon Turns Into a Long Journey

By Thomas Hackett | 9 Feb 2018

Have you ever attended the DesignCon show? I attended the recent event for the first time and was surprised by what I saw: tons of high-bandwidth coax cables, circuit boards, connectors, and other hardware—all harnessed to very expensive scopes and channel analyzers displaying perfect eye diagrams. This was definitely a show for hardware engineers. Walking around the show floor brought on an unexpected feeling...

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IP | IP integration | SDE | noise | Sigrity
New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions

By Dimitry Pavlovsky | 1 Feb 2018

The recent update of the AMBA® 5 ACE/AXI specification introduces a number of significant performance improvements which help to align the protocol to the more recent AMBA® 5 CHI (Coherent Hub Interface) specification. One of the most prominent features is introduction of atomic transactions. Before we take a close look at this new class of transactions, let’s look back in time. Previous generations of AMBA ACE/AXI...

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amba5 | ACE5 | AXI5 | AMBA
You Won't Believe Your Ears When Listening to Your Laptop

By PaulaJones | 31 Jan 2018

I wouldn't believe it if I hadn't heard it myself on a laptop in the Cadence booth at the Consumer Electronics Show ( CES) this year. Through a great innovation by our partner Dolby, you can now get surround sound on your laptop! You’ve probably been in a movie theater with Dolby’s latest innovation— Dolby Atmos . And maybe you’ve purchased a television in the last year with Dolby Atmos (it was a huge sensation at...

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CES | audio | HiFi | Tensilica
JEDEC UFS 3.0 Now Available in Cadence VIP Portfolio – For Mobile and Automotive Markets

By Thierry Berdah | 29 Jan 2018

The JEDEC UFS (Universal Flash Storage) started in 2011 with the v1.0 first specification version, supporting a bandwidth of 300 MB/s per lane. Since then JEDEC has been continuously releasing new UFS specification versions on top of the MIPI UniPro® and MIPI MPHY® evolving specs. UFS is now evolving to a new version of 3.0, reaching a total bandwidth of 2.4 GB/s. It seems that UFS keeps on slowly winning over eMMC in...

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Verification IP | UniPro | MIPI Alliance | JEDEC | automotive electronics | UFS | storage | MPHY
CCIX Coherency: Verification Challenges and Approaches

By Dimitry Pavlovsky | 24 Jan 2018

Cache coherency is not a new concept. Coherent architectures have existed for many generations of CPU and Interconnect designs. Verifying adherence to coherency rules in SoCs has always been one of the most complex challenges faced by verification engineers. Over the years, it became even more challenging with increasing number of cores in CPU clusters and introduction of the embedded L3 (level 3) cache to the coherent...

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Verification IP | ccix | SoC | coherency | System Verification
Book Your CES Meetings Now!

By PaulaJones | 4 Dec 2017

Want to see the exciting technology that is behind some of the biggest innovations at CES? Book a meeting now to visit the Cadence invitation-only suites at CES 2018, January 9-12, South Hall 2, Suite MP2577 (same location as last year). See Tensilic...

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USB 3.2—The USB Type-C Connector Finally Met its Match

By Jacek Duda | 19 Sep 2017

It’s only a week before the first event of USB Developer Days , a series of meetings for USB developers, where the USB 3.2 specification will be formally announced. Much like with any recent smartphone announcement, we know pretty much everything about the new standard before it’s formally announced. We know that the big news is the 20Gbps support, twice the performance of the previous (USB 3.1 Gen 2) standard, which...

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USB 3.0 | USB Type-C | DisplayPort | USB | USB 3.2 | power delivery | USB 3.1
Cadence IP Is Great for Automotive

By PaulaJones | 12 Sep 2017

If you’re designing chips for in-vehicle infotainment, in-cabin electronics, vision systems, digital noise reduction, and advanced driver assistance systems (ADAS), look at Cadence for the key IP to speed your design effort. We just announced that we have collaborated with a major foundry to produce an IP portfolio that’s ASIL-B ready and ASIL-C/D capable. See the press release for full details. Cadence IP is area...

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USB 3.0 | Design IP | DDR4 | LPDDR4 | PCI Express 3.0 | LPDDR | IP blocks | PCIe Gen4 | MIPI | DisplayPort | Automotive Ethernet | USB | memory IP | Ethernet | PCIe | 16nm | PCIe Gen3 | imaging | Ethernet PHYs | PCI
What’s New With Cadence PCI Express IP? Almost Everything!

By Sachin Dhingra | 22 Aug 2017

PCI-SIG Developer’s Conference 2017 was held in Santa Clara, California in June this year where several hundred customers from more than a hundred unique companies visited the conference. The next-generation PCI Express (PCIe) 5.0 specification was announced with plans for ratification in 2019. The announcement had a supporting quote by Cadence confirming our long-term commitment to developing products for PCIe interface...

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IP | TSMC | Gen4 | PCIe | 16nm | PCI Express 4.0 | 7nm | PCI-SIG
It's a Visual World

By Meera Collier | 22 Aug 2017

Here’s an experiment to try: in a quiet (but crowded) Auditorium, drop a stack of plates. Hypothesis: At the first splinters of the crash, all eyes will jerk to the source of the sound. You probably won’t get many people listening harder to find out what happened. Yes, our hearing can give us a lot of information, too—it can indicate direction, distance, magnitude, and even give some ideas about what happened ...

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controller IP | Design IP | IP | IP blocks | Embedded Vision Summit | vision processing | Jitendra Malik | IP design | Tensilica | vision | future of IP | Design IP and Verification IP | imaging | image processing
Happy Birthday Tensilica

By PaulaJones | 31 Jul 2017

Yes, it’s Tensilica’s birthday! Twenty years ago today, on July 31, 1997, Tensilica was officially incorporated by Chris Rowen, who I knew from our Synopsys days when he was VP of the Design Reuse Business Unit. I started working with Tensilica (as a PR consultant) when there were eight people in the office next to the Duke of Edinburgh pub on Wolfe road in Cupertino. I became a Tensilica employee in 2002, and worked...

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DSP | Chris Rowen | HiFi | Tensilica | vision
What Will It Take to Bring DNN to Embedded?

By PaulaJones | 12 Jul 2017

If you missed Michelle Mao’s presentation at the recent Autosens conference in Detroit, “What Will It Take to Bring DNN to Embedded?”, you missed an important evaluation of how designers can do four fundamental things to lower the power budget and bring deep neural networks (DNNs) to embedded systems: Optimize the network architecture Optimize the problem definition Minimize the number of bits per computation...

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architecture | Vision C5 | Tensilica | vision | dnn | CNN | neural nets | embedded
New VIP for ARM AMBA 5 CHI Issue B

By Priya Balasubramanian | 19 Jun 2017

In coordination with the announcement of the new ARM® AMBA® 5 Coherent Hub Interface Issue B, Cadence is announcing the availability of its AMBA 5 CHI Issue B Verification IP (VIP) to address the complexity challenges of enterprise SoC development for...

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Verification IP | VIP | AMBA | ARM | CHI VIP
USB Type-C: Let’s Get Real

By Thomas Hackett | 5 Apr 2017

Have you tried a product incorporating the new USB Type-C port? Do you wonder how well it works? I recently bought a new laptop and monitor that support this interface. In fact, Type-C is the only port on those devices. Image courtesy Austin Event Photography I’ve been looking forward to the promise of a single, all-encompassing port ever since I wrote Why USB 3.0 Will Drive SoC Verification back in 2013. Well...

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Design IP | USB Type-C | USB-IF | USB | Type-C | Design IP and Verification IP | USB 3.1
Memory Trends for Automotive Markets

By Priya Balasubramanian | 8 Mar 2017

Remember automobiles from a few years ago? They were pretty simple machines with lots of small microprocessors distributed across the whole vehicle and doing fairly simple tasks. Semiconductors have been in automobiles for several years, of course, with simple 8- and 16-bit microcontrollers performing functions like Anti-lock Braking (ABS). But today’s automobiles are a different beast. They incorporate several compute...

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Design IP | IP | Memory | LPDDR4 | LPDDR | DIP | memory IP | Design IP and Verification IP | memories
Three New Memory Trends in Enterprise Data Centers

By Priya Balasubramanian | 22 Feb 2017

You might have seen the graph below about the increase in monthly internet traffic around the world. Ever wondered what was causing it? If you think all that traffic is simply due to people binge-watching House of Cards on Netflix, or uploading the...

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Design IP | Memory | DDR4 | flash | memory IP | DDR | memories
Bluetooth 5: Making Your Smart Home a Reality

By Priya Balasubramanian | 5 Dec 2016

We all know the futuristic vision of the world just around the corner. The vision where we tell our smart home that we’ve just left work at the end of a long day, and we’re heading home. Our home then tells the thermostat to warm up or cool down, lights to turn on, and the oven to start baking the lasagna we left in it that morning. We arrive to a warm, brightly lit home, and hot, freshly cooked food. You’ve got the...

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Verification IP | Bluetooth Low Energy | IoT | VIP | BLE | Tensilica | design | mobile | and Verification IP | Bluetooth 5 | Bluetooth 5.0 | Smart Home
Genie in a Mouse Click: Indago Protocol Debug App

By Priya Balasubramanian | 2 Nov 2016

Do you remember what life was like before the internet and smart phones? If you wanted to find information about something, you had to go to the library and find a book that could answer your question, which usually meant a delay of anything from a few hours to several days. Then the internet happened, and the world as we know it changed forever. Smart phones came along, and brought with them a new kind of freedom and...

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Productivity Tool | Verification IP | and Verification IP' | VIP | Indago Protocol Debug App | design | 'Tensilica

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