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Is the Role of Test Chips Changing at Advanced Foundry Nodes?

By TomWong | 15 Jul 2019

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long been making test chips to...

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Design IP | IP | cadence | PCIe Gen4 | IP integration | ip cores | Ethernet | semiconductor IP | PCI Express
How to Verify Performance of Complex Interconnect-Based Designs?

By Thierry Berdah | 14 Jul 2019

With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions...

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Verification IP | Interconnect Workbench | Interconnect Validator | SoC | Performance modeling | AMBA | ATP | ARM | System Verification
AMBA Adaptive Traffic Profiles: Addressing The Challenge

By DimitryP | 9 Jul 2019

Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and autonomous driving. With increased number of SoC components, such as CPUs, GPUs, accelerators and I/O devices, comes increased demand to correctly model interoperability of various components. Traditional simulation of complex...

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Adaptive Traffic Profiles | Performance modeling | AMBA | ATP
SemiEngineering Article: Why IP Quality Is So Difficult to Determine

By TomWong | 7 Jun 2019

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends upon how and where it is used and in part, because even the best IP may work better in one system than another—even in chips developed by the same vendor. So, how do you measure IP quality and why it is so complicated? The answer depends on who is asking. Most of the time, the definition of IP quality depends on...

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IP | cadence | IP blocks | Automotive Ethernet | ip cores | Tensilica | semiconductor IP | Design IP and Verification IP
Designing for the Future - Managing the Impact of Moore's Law

By TomWong | 15 May 2019

With Moore’s Law, the industry assumes that when you go from one geometry to the next finer node, you will have performance gains. All this is automatic. Chip designers have tried to leverage improvements in process technology to get performance improvements for many years now. Let’s examine whether or not this assumption is still valid. When we were at more mature technologies, such as 90nm to 65nm, there may have...

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Design IP | IP | LPDDR | PCIe Gen4 | MIPI | USB | SerDes
NVMe 2019 Developer's Conference: NVMe 1.4 Is Almost Here, and Enterprise and Cloud Adoption Is Poised for Mainstream Adoption

By Lana Chan | 21 Mar 2019

Unlike previous years, the annual NVM Express Developer’s Conference was held in Fremont instead of San Jose. A well-attended event for the 120+ member consortium, this was a fantastic opportunity for developers to network and discuss new developments and how to keep NVMe simple, fast and scalable. Robust growth across client, enterprise and cloud segments was shown with data from Forward Insights. With a hockey stick...

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Verification IP | Enterprise | NVM Express | PCIe Gen4 | NVMe | VIP | cloud | PCIe | PCI Express | TripleCheck
NXP Introduces Tensilica HiFi 4 DSP-based Platforms to Secure IoT Edge Devices

By PaulaJones | 10 Oct 2018

Trust. Privacy. Confidentiality. These are three important concerns for designers of IoT edge devices. Today NXP announced that they are addressing these concerns with two new platforms that feature secure execution environment (SEE) to give developers access to “unprecedented” security capabilities. These platforms provide a multi-layered, hardware-enabled protection scheme to secure IoT edge devices and cloud-to...

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IP | IoT | HiFi | ip cores | Tensilica | semiconductor IP | Internet of Things
Evolution of DisplayPort

By Steve Wang | 27 Aug 2018

In 2006, the Video Electronics Standards Association (VESA) designed a new display interface to compete with HDMI: the DisplayPort. Since then DisplayPort has become more and more popular in the computer world. Let’s take a look at the evolutio...

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Verification IP | DisplayPort | verification
Is Ethernet Ready for the Automotive Market?

By Thierry Berdah | 19 Aug 2018

Consumer demand for advanced driver assistance and infotainment features are on the rise, opening up a new market for advanced Automotive systems. Automotive Ethernet allows to support more complex computing needs with the use of an Ethernet-based network for connections between in-vehicle electronic systems. The number of vehicles with automotive Ethernet began picking up over the last years, at which time BMW,...

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Verification IP | VIP | Ethernet standards | Automotive Ethernet | IEEE 802.3 | Ethernet | TSN | Ethernet PHYs
Cadence Tensilica Fusion F1 DSP Stars in NB IoT Applications

By PaulaJones | 2 Jul 2018

Did you make it to MWC Shanghai? I didn’t, but I read about what was hot – narrowband (NB) IoT. Three of Cadence’s customers had Tensilica Fusion F1 DSP demos on the show floor. Xinyi Information Technology, a China-based company, showed off the first single-core modem that integrates a CMOS power amplifier with the modem. Their Marconi X1 modem features an NB-IoT protocol stack from Huachang Technology, who was able...

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DSP | IoT | Fusion | ip cores | Tensilica | nb-iot
Chip Dis-integration

By TomWong | 27 Jun 2018

I was asked the following question recently. No longer are we seeing increasing amounts of functionality being crammed into chips, except under very special circumstances. Chips today are trending towards the leaner side. Is this only when power is a primary concern? Does this apply to all technology nodes or only to larger ones? What about pins – I/O has often been the limiter. What impact will this have on IP? Will...

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chiplets | IoT | Design IP and Verification IP | moore's law | 2.5D interposer
PCI-SIG Developer's Conference: What's New with Gen 5 and When Will it be Adopted?

By Lana Chan | 6 Jun 2018

The release of PCIe 4.0 rev 1.0 in October 2017 was anticlimactic after the announcement of PCIe 5.0 rev 0.3 at last year’s PCI-SIG DevCon. Fast forward, this year’s DevCon has kicked off and the SIG is clearly demonstrating its commitmen...

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controller IP | Verification IP | PCIe Gen4 | PHY | PCIe | PCIe Gen5 | verification
How We Developed and Tested a Prototype DDR5 Interface in Silicon Based on a Preliminary Version of the DDR5 Standard

By Marcgr | 1 May 2018

We’re thrilled to have announced our prototype 7nm DDR5 IP silicon based on a preliminary version of the DDR5 standard at this week's TSMC Technology Symposium. This has been a huge amount of work from the DDR teams at Cadence and sets a landmark for the adoption of a new memory standard in the industry. This has been quite an experience for us, starting in 2017 when we developed the prototype DDR5 PHY and DDR5 Controller...

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DDR Controller | Verification IP | ddr5 | DDR4 | TSMC Tech Symposium | TSMC | DDR | DDR PHY
New AMBA 5 ACE/AXI Specification and Its Support in Cadence ACE/AXI VIP

By DimitryP | 3 Apr 2018

As discussed in the previous installments of the blog, the recent update of the AMBA ® 5 ACE/AXI specification introduced several performance improvement features which align the AMBA5 ACE/AXI protocol with AMBA 5 CHI (Coherent Hub Interface) specification. Among them is the new class of atomic transactions, discussed in-depth previously. Another new transaction class includes the new cache stash transactions which...

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amba5 | Verification IP | ACE VIP | AXI VIP | AMBA
NVMe Express 1.3: Addressing the Storage Needs of the Data Revolution from Enterprise to Client

By Lana Chan | 2 Apr 2018

The amount of data we are generating and consuming has exploded in recent years. Social media, applications, multimedia streaming, 24-hour connectivity has us talking about Zettabytes of data in the data center that folks want to not only store, but analyze and access rapidly. SSDs were great to address mechanical inefficiencies of HDD. However, the constraints of the SCSI protocol still meant that you can only address...

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Verification IP | NVM Express | NVMe | IoT | VIP | cloud | big data | storage | PCIe | PCI Express | data centers
Why Software-Based GPS Is Great for Location-Based IoT Applications

By PaulaJones | 27 Feb 2018

At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo of a software-based GPS receiver from Galileo Satellite Navigation running off a Cadence Tensilica Fusion F1 DSP. It’s a very impressive demo—come by...

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Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

By tomhackett | 23 Feb 2018

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would anyone care? To answer that, let's start with a quiz from the transportation industry. How many shipping containers are currently in transit around the world? It turns out that no one knows for sure, but the best guess is that there are about 20 million containers in service today. And it's a safe bet that those containers are carrying...

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Galileo | GPS | IoT | Tensilica DSPs
New AMBA 5 ACE/AXI Specification: More About Atomic Transactions

By DimitryP | 22 Feb 2018

As discussed in the previous installment of this blog, a new class of atomic transactions was introduced in the AMBA® 5 ACE/AXI specification to make operations at the remote locations more streamlined and efficient. We have considered an example of AtomicStore transaction with ADD operation and discussed why it was more efficient than relying on the older semaphore-like exclusive operations. In this installment of the...

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amba5 | ACE5 | AXI5 | Atomic Transactions
See You in Barcelona at MWC!

By PaulaJones | 12 Feb 2018

I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never fails to amaze me. This year’s theme is “Creating a Better Future” and I can’t think of a better theme for Cadence – our Tensili...

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DSP | IP | Mobile World Congress | ip cores | Tensilica | vision | imaging
What I Learned About System Design Enablement at DesignCon

By tomhackett | 9 Feb 2018

While attending the recent DesignCon show for the first time, I was struck by the many displays of cables, connectors, boards, and various kinds of test equipment (you can read about the impact this had on me in my previous post, A Walk Through DesignCon Turns Into a Long Journey ). There was so much hardware, in fact, that I felt like I was walking through a giant Fry’s store. The impression was so strong that my first...

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IP | IP integration | SDE | Sigrity | system design enablement
A Walk Through DesignCon Turns Into a Long Journey

By tomhackett | 9 Feb 2018

Have you ever attended the DesignCon show? I attended the recent event for the first time and was surprised by what I saw: tons of high-bandwidth coax cables, circuit boards, connectors, and other hardware—all harnessed to very expensive scopes and channel analyzers displaying perfect eye diagrams. This was definitely a show for hardware engineers. Walking around the show floor brought on an unexpected feeling...

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IP | IP integration | SDE | noise | Sigrity
New AMBA 5 ACE/AXI Specification: Rationale for Atomic Transactions

By DimitryP | 1 Feb 2018

The recent update of the AMBA® 5 ACE/AXI specification introduces a number of significant performance improvements which help to align the protocol to the more recent AMBA® 5 CHI (Coherent Hub Interface) specification. One of the most prominent features is introduction of atomic transactions. Before we take a close look at this new class of transactions, let’s look back in time. Previous generations of AMBA ACE/AXI...

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amba5 | ACE5 | AXI5 | AMBA
You Won't Believe Your Ears When Listening to Your Laptop

By PaulaJones | 31 Jan 2018

I wouldn't believe it if I hadn't heard it myself on a laptop in the Cadence booth at the Consumer Electronics Show ( CES) this year. Through a great innovation by our partner Dolby, you can now get surround sound on your laptop! You’ve probably been in a movie theater with Dolby’s latest innovation— Dolby Atmos . And maybe you’ve purchased a television in the last year with Dolby Atmos (it was a huge sensation at...

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CES | audio | HiFi | Tensilica
JEDEC UFS 3.0 Now Available in Cadence VIP Portfolio – For Mobile and Automotive Markets

By Thierry Berdah | 29 Jan 2018

The JEDEC UFS (Universal Flash Storage) started in 2011 with the v1.0 first specification version, supporting a bandwidth of 300 MB/s per lane. Since then JEDEC has been continuously releasing new UFS specification versions on top of the MIPI UniPro® and MIPI MPHY® evolving specs. UFS is now evolving to a new version of 3.0, reaching a total bandwidth of 2.4 GB/s. It seems that UFS keeps on slowly winning over eMMC in...

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Verification IP | UniPro | MIPI Alliance | JEDEC | automotive electronics | UFS | storage | MPHY
CCIX Coherency: Verification Challenges and Approaches

By DimitryP | 24 Jan 2018

Cache coherency is not a new concept. Coherent architectures have existed for many generations of CPU and Interconnect designs. Verifying adherence to coherency rules in SoCs has always been one of the most complex challenges faced by verification engineers. Over the years, it became even more challenging with increasing number of cores in CPU clusters and introduction of the embedded L3 (level 3) cache to the coherent...

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Verification IP | ccix | SoC | coherency | System Verification

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