Tensilica, Design, and Verification IP Blogs

As the de facto IO interconnect technology, PCIe has commendably addressed the performance bottleneck at the IO interface by doubling the bandwidth support every 3-4 years over the course of 5 generations of the specification and with Gen 6 at 64GT/s in the works. However, the datafication of everything requires that the raw data be processed and/or harvested for meaningful information. The high computational workloads...

Draft 1.0 of 802.3ck, also known as 100G per lane, was finally published by IEEE in Dec 2019. This draft provided the standardization of higher lane speed support for backplane systems, including 3 speed mode variations: 100G, 200G, and 400G. Backplane Ethernet speed is increasing, evolving from 10G, 25G, 50G, to current 100G on a single SerDes lane within less than 10 years, offering unprecedented capacity for the datacenter...

USB is one of the most widely used interfaces in the PC market for more than 20 years. Though it remains the same form in laptops and servers, it never stops its evolution in terms of capacity and speed. Embedded USB2.0, known as eUSB2, was created to address the concerns of power efficiency and portability. Although eUSB2 largely reuses USB2.0 protocol layer, the verification of eUSB2 can be never thought of as a miniature...

Since 2013, we have seen the HBM specifications being released by JEDEC and companies announcing in the same month HBM products just like magic. How can these companies have a silicon-proven product altogether with newly announced official specifications? What is the secret process they use in order to be constantly first-in-market with these new technologies? And more important, what can YOU do in order to also be such...

Verifying lane adapter state machine in a router design is quite an involved task and needs verification from several aspects including that for its link training functionality. The diagram below shows two lane adapters connected to each other and each going through the link training process. Each training sub-state transition is contingent on conditions for both transmission and reception of relevant ordered sets...

USB4 can simultaneously tunnel USB3, PCIe and DisplayPort native protocol traffic through a hierarchy of USB4 routers. The key to tunneling of these protocols is routing table programmed at each ingress adapter. An entry of a routing table maps an incoming HopID, called Input/Ingress HopID to a corresponding pair of Output/Egress Adapter and Egress/Output HopID. The responsibility of programming routing tables lies...

PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus is predominantly around the latest updates for PCIe Gen 5 which its version 1.0 specification was just released this year in May. A series of presentations provided by PCI-SIG on the day 1 with comprehensive information covering all aspects of Gen 5 specification, including protocol, logical, electrical, compliance updates. On the day 2 ...

The PCI-SIG finalized the PCIe 4.0 specification with doubling the data to 16GT/s from 8GT/s in PCIe 3.0 in 2017. Products implementing this technology have begun to hit the market in 2019. Earlier this year, AMD announced it X570 chipset would support the PCIe 4.0 interface and Phison also introduced the world’s first PCIe 4.0 SSD. With the increasing companies are working on PCIe 4.0 related product development, Cadence...

PCIe has been widely adopted in the electronics industry since its first debut in 2003 (PCIe 1.0 standard release) for wide breach of applications, from Data Center Server, Networking, to Mobile, AI/ML, Automotive, IoT, and many others…. It’s a versatile, high-performance, robust, mature interconnect standard with full “backward compatibility” (e.g., a PCIe 3.0 device can still function well in a PCIe 4.0 system) which...

Verification of a USB4 router design is not just about USB4 but also about the inclusion of the three other major protocols namely, USB3, DisplayPort (DP), and PCI Express (PCIe). These protocols can be simultaneously tunneled through a USB4 router. Put in simple terms, such tunneling involves the conversion of the respective native USB3, DP, or PCIe protocol traffic into the USB4 transport layer packets, which are tunneled...

Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs. Semiconductor designers have long been making test chips to...

With more and more SoCs employing sophisticated interconnect IP to link multiple processor cores, caches, memories, and dozens of other IP functions, the designs are enabling a new generation of low-power servers and high-performance mobile devices. The complexity of the interconnects and their advanced configurability contributes to already formidable design and verification challenges which lead to the following questions...

Modern systems-on-a-chip (SoCs) continue to increase in complexity, adding more components and calculation power to accommodate new performance-hungry applications such as machine learning and autonomous driving. With increased number of SoC components, such as CPUs, GPUs, accelerators and I/O devices, comes increased demand to correctly model interoperability of various components. Traditional simulation of complex...

Differentiating good IP from mediocre or bad IP is getting more difficult, in part because it depends upon how and where it is used and in part, because even the best IP may work better in one system than another—even in chips developed by the same vendor. So, how do you measure IP quality and why it is so complicated? The answer depends on who is asking. Most of the time, the definition of IP quality depends on...

With Moore’s Law, the industry assumes that when you go from one geometry to the next finer node, you will have performance gains. All this is automatic. Chip designers have tried to leverage improvements in process technology to get performance improvements for many years now. Let’s examine whether or not this assumption is still valid. When we were at more mature technologies, such as 90nm to 65nm, there may have...

Unlike previous years, the annual NVM Express Developer’s Conference was held in Fremont instead of San Jose. A well-attended event for the 120+ member consortium, this was a fantastic opportunity for developers to network and discuss new developments and how to keep NVMe simple, fast and scalable. Robust growth across client, enterprise and cloud segments was shown with data from Forward Insights. With a hockey stick...

Trust. Privacy. Confidentiality. These are three important concerns for designers of IoT edge devices. Today NXP announced that they are addressing these concerns with two new platforms that feature secure execution environment (SEE) to give developers access to “unprecedented” security capabilities. These platforms provide a multi-layered, hardware-enabled protection scheme to secure IoT edge devices and cloud-to...

In 2006, the Video Electronics Standards Association (VESA) designed a new display interface to compete with HDMI: the DisplayPort. Since then DisplayPort has become more and more popular in the computer world. Let’s take a look at the evolutio...

Consumer demand for advanced driver assistance and infotainment features are on the rise, opening up a new market for advanced Automotive systems. Automotive Ethernet allows to support more complex computing needs with the use of an Ethernet-based network for connections between in-vehicle electronic systems. The number of vehicles with automotive Ethernet began picking up over the last years, at which time BMW,...

Did you make it to MWC Shanghai? I didn’t, but I read about what was hot – narrowband (NB) IoT. Three of Cadence’s customers had Tensilica Fusion F1 DSP demos on the show floor. Xinyi Information Technology, a China-based company, showed off the first single-core modem that integrates a CMOS power amplifier with the modem. Their Marconi X1 modem features an NB-IoT protocol stack from Huachang Technology, who was able...

I was asked the following question recently. No longer are we seeing increasing amounts of functionality being crammed into chips, except under very special circumstances. Chips today are trending towards the leaner side. Is this only when power is a primary concern? Does this apply to all technology nodes or only to larger ones? What about pins – I/O has often been the limiter. What impact will this have on IP? Will...

The release of PCIe 4.0 rev 1.0 in October 2017 was anticlimactic after the announcement of PCIe 5.0 rev 0.3 at last year’s PCI-SIG DevCon. Fast forward, this year’s DevCon has kicked off and the SIG is clearly demonstrating its commitmen...

We’re thrilled to have announced our prototype 7nm DDR5 IP silicon based on a preliminary version of the DDR5 standard at this week's TSMC Technology Symposium. This has been a huge amount of work from the DDR teams at Cadence and sets a landmark for the adoption of a new memory standard in the industry. This has been quite an experience for us, starting in 2017 when we developed the prototype DDR5 PHY and DDR5 Controller...

As discussed in the previous installments of the blog, the recent update of the AMBA ® 5 ACE/AXI specification introduced several performance improvement features which align the AMBA5 ACE/AXI protocol with AMBA 5 CHI (Coherent Hub Interface) specification. Among them is the new class of atomic transactions, discussed in-depth previously. Another new transaction class includes the new cache stash transactions which...

The amount of data we are generating and consuming has exploded in recent years. Social media, applications, multimedia streaming, 24-hour connectivity has us talking about Zettabytes of data in the data center that folks want to not only store, but analyze and access rapidly. SSDs were great to address mechanical inefficiencies of HDD. However, the constraints of the SCSI protocol still meant that you can only address...