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Arm Zena CSS – Accelerating Chiplet-Based SoC Design for AI-Defined Vehicles

Cadence is collaborating with Arm on their groundbreaking first-generation compute…

Robert
• 6 min read
virtual prototyping , ucie , featured , chiplet , virtual platform

Symmetric Multiprocessing (SMP) RTOS on Xtensa Multicore

An increasing number of multi-threaded embedded applications want to leverage multicore…

Nayan Gaywala
• 8 min read
featured , Symmetric Multiprocessing , SMP , Tensilica , FreeRTOS

Accelerate Your Automotive, Consumer, and Data Center Semiconductor Projects

Semiconductor innovation is the driving force behind groundbreaking advancements…

Corporate
• 3 min read
Automotive , featured , CES , Tensilica
SoC and IP

Latest blogs

Redefining SoC Design: The Shift to Secure Chiplet-Based Architectures

The semiconductor industry is undergoing a paradigm shift from monolithic system…

Moshiko Emmer
• 5 min read
security , Automotive , chiplets , physical ai , SoC

Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos

As we move through 2025, the momentum generated by Cadence continues to energize…

Joe C
• 2 min read
PCIe 7.0 , PCIe , PCI-SIG

Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding

In our previous blog, we discussed the fundamentals of time-of-flight (ToF) technology…

SriramK
• 5 min read
IP , vision processing , IoT , Tensilica DSPs , ip cores , Vision DSPs , Tensilica , vision , semiconductor IP , imaging , image processing

Arm Zena CSS – Accelerating Chiplet-Based SoC Design for AI-Defined Vehicles

Cadence is collaborating with Arm on their groundbreaking first-generation compute…

Robert
• 6 min read
virtual prototyping , ucie , featured , chiplet , virtual platform , CSA , compute subsystem , SDV , css , ARM , helium , AI

Enhancing Edge AI with the Newest Class of Processor: Tensilica NeuroEdge 130 AI

Artificial intelligence is rapidly expanding its reach into embedded systems and…

SriramK
• 3 min read
DSP , IP , IoT , Tensilica DSPs , ip cores , Tensilica , semiconductor IP , AI

Boosting AI Performance with CXL

As AI applications rapidly advance, AI models are being tasked with processing massive…

Vanessa Do
• 3 min read
CXL , IP , controller , PCIe

Linux-Based Audio Platform with Cadence Tensilica HiFi 5

A Linux-based audio platform with Cadence Tensilica HiFi 5 enables rapid algorithm…

Vinod Khera
• 3 min read
hifi 5 , IP , Tensilica , HiFi 5s , HiFi Audio

CadenceLIVE 2025: The Field Guide for Defense Digital Engineering

Modern microelectronics is a new operating theater for many in the Defense Industrial…

Adam Sherer
• 2 min read
cadencelive , defense

Time-of-Flight Decoding with Tensilica Vision DSPs

Today, let's break down time-of-flight (ToF) and how Tensilica Vision DSPs can be…

SriramK
• 1 min read
IP , Consumer Electronics , cadence , video , Tensilica DSPs , ip cores , Tensilica , vision , semiconductor IP , cadencelive , imaging , image processing

Cadence San Jose Hosts JEDEC LPDDR Task Group Meeting

Low-power DDR ( LPDDR ) SDRAM has been one of the most widely used memories in the…

Shyam Sharma
• 2 min read
Verification IP , Design IP , IP , VIP , JEDEC , LPDDR PHY IP , DRAM , LPDDR Controller IP , Design IP and Verification IP , Lpddr6

HBM4 Boosts Memory Performance for AI Training

The recent HBM4 specification announced by JEDEC is great news for developers of…

Frank Ferro
• 2 min read
JEDEC , hbm4 , memory IP , AI training , data centers

Functional Safety in a Disaggregated World

We are witnessing a dramatic rise in disaggregation and a lot of discussion around…

MBhatnagar
• 5 min read
Automotive , functional safety , fusa

How Physical AI Is Redefining the Automotive Industry

The automotive world is experiencing a groundbreaking transformation, with technology…

Reela
• 5 min read
Automotive , IP , ev , physical ai , Software-Defined Vehicles , ADAS , AI

Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process

We are thrilled to announce that Cadence has successfully demonstrated first-pass…

MBhatnagar
• 2 min read
ucie , PHY , samsung foundry

AI's Rapid Growth: The Crucial Role of High Bandwidth Memory

System efficiency is dictated by the performance of crucial components. For AI hardware…

Subash Peddu
• 5 min read
Design IP , IP , HBM

Symmetric Multiprocessing (SMP) RTOS on Xtensa Multicore

An increasing number of multi-threaded embedded applications want to leverage multicore…

Nayan Gaywala
• 8 min read
featured , Symmetric Multiprocessing , SMP , Tensilica , FreeRTOS , Xtensa , multicore , RTOS , multiprocessing

eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview

When developing system-on-chip (SoC) solutions, the key features often minimize size…

DavidShin
• 3 min read
Design IP , cadence , PHY , USB-IF , USB , SoC , USB 2.0

Enkl Sound Elevates Audio Tech with Tensilica HiFi DSP for Unmatched Excellence

In the rapidly evolving world of audio technology, Enkl Sound Copenhagen emerges…

Vinod Khera
• 3 min read
Sound , Hearable , wearables , Tensilica HiFi DSP , Bluetooth Speakers

Accelerate the Photonic IC Design with Cadence EPDA Environment

Do you believe the existing semiconductor methodologies will adequately support the…

Vinod Khera
• 4 min read
Photonic IC Design , EPDA Environment , photonics

Accelerate Your Automotive, Consumer, and Data Center Semiconductor Projects

Semiconductor innovation is the driving force behind groundbreaking advancements…

Corporate
• 3 min read
Automotive , featured , CES , Tensilica

Cadence Transforms Chiplet Technology with First Arm-Based System Chiplet

Cadence has achieved a significant milestone by designing and taping out its first…

Moshiko Emmer
• 4 min read
Automotive , ucie , featured , chiplets , NoC , lpddr5 , ARM

Simulating Multiple Cadence DSPs as Multiple x86 Processes

An increasing number of embedded designs are multi-core systems. At the pre-silicon…

Nayan Gaywala
• 4 min read
Tensilica , Xtensa , SystemC , multicore , simulation , multiprocessing

Redefining Hearing Aids with Cadence DSPs

Hearing is one of the most essential senses for engaging with the world. It enables…

Vinod Khera
• 4 min read
Tensilica DSPs , HiFi DSP , Fusion DSP Family , Hearing Aids

Driving Innovation: Cadence's Cutting-Edge IP on TSMC's N3 Node

Staying ahead of the curve is essential to meeting customer needs. Cadence has consistently…

Frank Ferro
• 2 min read
ucie , Memory , LPDDR , ip cores , PCIe , DDR , GDDR7

The Future of Driving: How Advanced DSP is Shaping Car Infotainment Systems

As vehicles transition into interconnected ecosystems, artificial intelligence and…

Reela
• 5 min read
Automotive , DSP , infotainment , Tensilica , HiFi 5s

Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem

Cadence tapes out 32G UCIe interface IP for high speed, highly efficient chiplet…

MBhatnagar
• 4 min read
ucie , IP , die-to-die

Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA

Today's high-performance computing systems often require the designer to instantiate…

Nayan Gaywala
• 4 min read
AXI , Tensilica , Xtensa , FPGA

DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers

The demand for higher-performance computing is greater than ever. Cutting-edge applications…

Kos Gitchev
• 2 min read
ddr5 , Design IP , IP , gddr6 , PHY , 3nm , MRDIMM , GDDR , memory IP , Denali , Design IP and Verification IP , DDR
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