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Featured

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
Sheryl G 7 Oct 2025 • 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
MBhatnagar 22 Sep 2025 • 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Arm Zena CSS – Accelerating Chiplet-Based SoC Design for AI-Defined Vehicles

Cadence is collaborating with Arm on their groundbreaking first-generation compute…

Robert
Robert 4 Jun 2025 • 6 min read
virtual prototyping , ucie , featured , chiplet , virtual platform
SoC and IP

Latest blogs

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G 7 Oct 2025 • 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink , ECOC , Ultra Ethernet

Accelerate Automotive System Design with Cadence AI-Driven DSPs

The automotive industry is on the brink of a transformative era powered by intelligence…

Vinod Khera 6 Oct 2025 • 6 min read
Automotive , infotainment , autonomy , In-cabin sensing , lidar , Xtensa CPU , radar , Tensilica , vision , ADAS

A Hybrid Subsystem Architecture to Elevate Edge AI

The world of artificial intelligence is moving beyond the cloud and into our everyday…

SriramK 2 Oct 2025 • 4 min read
controller IP , DSP , cadence , NeuroEdge 130 , IoT , Tensilica DSPs , SoC , ip cores , Tensilica , semiconductor IP , AICP

From 12 Hours to 2: How AI Accelerates Automotive Quality Assurance

In the fast-paced world of Industry 4.0, quality assurance (QA) is no longer just…

Anika Sunda 1 Oct 2025 • 2 min read
Automotive , Regression , Verisium Manager

Ensuring End-to-End Traceability for Safety-Critical Applications

There is now a direct interface between the Midas Safety Platform and popular requirements…

Robert 30 Sep 2025 • 4 min read
Requirement Management System , Safety Solution , DOORS , functional safety , RMS , Safety , Product Lifecycle Management , Safety Analysis , JIRA , Traceability , Jama , Polarion , PLM , Codebeamer , Safety Compliance

Boosting AI Performance with CXL

AI workloads are outpacing traditional memory architectures—but CXL®︎ offers a smarter…

Vanessa Do 22 Sep 2025 • 3 min read
CXL , IP , controller , PCIe

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar 22 Sep 2025 • 3 min read
ucie , Design IP , featured , TSMC , die-to-die , HPC , AI

Cadence Powers AI Infra Summit '25: Memory, Interconnect, and Interface Focus

AI is driving a new semiconductor renaissance—it's no longer just a workload, but…

Joe C 16 Sep 2025 • 2 min read
controller IP , ucie , Design IP , IP , Memory , AISummit , 224G-LR , HBM , hbm4 , memory IP , Ethernet , AI training , Ethernet PHYs , UALink , AI , data centers , AIInfraSummit

Design for Reliability: Midas Safety Platform

In today’s safety-critical applications—automotive, aerospace, industrial automation…

Atreya 10 Sep 2025 • 3 min read
Automotive , semiconductor IP , Internet of Things

Rethinking AI Infrastructure: The Rise of PCIe Switches

Boring? Think Again. PCIe Switches Are the Hidden Power Behind AI When thinking of…

Vanessa Do 2 Sep 2025 • 5 min read
controller IP , CXL , PCIe controller , PCIe Gen4 , pcie4 , PCIe 7.0 , IP design , PCIe , future of IP , PCIe PHY , PCIe 6.0 , PCI Express

Cadence Drives Next-Gen Memory and Connectivity at FMS 2025

As AI data centers continue to scale up and out to accommodate increasingly compute…

Vanessa Do 27 Aug 2025 • 1 min read
PCIe controller , ucie , HBM , PCIe 7.0 , PCIe , DDR IP , UALink , PCIe 6.0 , PCI Express

CNNs and Transformers: Decoding the Titans of AI

In the rapidly advancing field of artificial intelligence, two neural network architectures…

SriramK 13 Aug 2025 • 8 min read
IP , ip cores , Tensilica , SSG , semiconductor IP , AI

From "What-If" to "What-Is": Cadence IP Validation for Silicon Platform Success

Data rates are escalating with seemingly no end in sight due to the insatiable demand…

Joe C 12 Aug 2025 • 2 min read
DIP , ip validation , post silicon , full subsystem , verification

Next-Gen Memory Starts Here: Cadence at the Future of Memory and Storage

FMS: the Future of Memory and Storage is fast approaching (August 5-7 at the Santa…

GautamS 1 Aug 2025 • 2 min read
ddr5 , Design IP , Memory , FMS , PCIe , SerDes , UALink

Designing the AI Factories: Unlocking Innovation with Intelligent IP

The rapid evolution of artificial intelligence (AI) is reshaping the technological…

Reela Samuel 16 Jul 2025 • 3 min read
IP , AI Factories , memory IP , semiconductor IP , Memory Modules , AI

LPDDR6: A New Standard and Memory Choice for AI Data Center Applications

LPDDR SDRAM, initially developed for low-power mobile devices such as smartphones…

Frank Ferro 14 Jul 2025 • 2 min read
ddr5 , LPDDR , hbm4 , LPDDR Controller IP , lpddr5x , AI training , Lpddr6

Role of Time-of-Flight Sensors in Automotive

In recent posts, we've explored the foundational aspects of Time-of-Flight (ToF)…

SriramK 9 Jul 2025 • 5 min read
Automotive , IP , Tensilica DSPs , ip cores , Tensilica , vision , Xtensa , semiconductor IP , ADAS , image processing

Redefining SoC Design: The Shift to Secure Chiplet-Based Architectures

The semiconductor industry is undergoing a paradigm shift from monolithic system…

Moshiko Emmer 23 Jun 2025 • 5 min read
security , Automotive , chiplets , physical ai , SoC

Cadence Leads the Way at PCI-SIG DevCon 2025 with Groundbreaking PCIe 7.0 Demos

As we move through 2025, the momentum generated by Cadence continues to energize…

Joe C 16 Jun 2025 • 2 min read
PCIe 7.0 , PCIe , PCI-SIG

Time-of-Flight Decoding with Tensilica Vision DSPs - AI's Role in ToF Decoding

In our previous blog, we discussed the fundamentals of time-of-flight (ToF) technology…

SriramK 5 Jun 2025 • 5 min read
IP , vision processing , IoT , Tensilica DSPs , ip cores , Vision DSPs , Tensilica , vision , semiconductor IP , imaging , image processing

Arm Zena CSS – Accelerating Chiplet-Based SoC Design for AI-Defined Vehicles

Cadence is collaborating with Arm on their groundbreaking first-generation compute…

Robert 4 Jun 2025 • 6 min read
virtual prototyping , ucie , featured , chiplet , virtual platform , CSA , compute subsystem , SDV , css , ARM , helium , AI

Enhancing Edge AI with the Newest Class of Processor: Tensilica NeuroEdge 130 AI

Artificial intelligence is rapidly expanding its reach into embedded systems and…

SriramK 19 May 2025 • 3 min read
DSP , IP , IoT , Tensilica DSPs , ip cores , Tensilica , semiconductor IP , AI

Linux-Based Audio Platform with Cadence Tensilica HiFi 5

A Linux-based audio platform with Cadence Tensilica HiFi 5 enables rapid algorithm…

Vinod Khera 5 May 2025 • 3 min read
hifi 5 , IP , Tensilica , HiFi 5s , HiFi Audio

CadenceLIVE 2025: The Field Guide for Defense Digital Engineering

Modern microelectronics is a new operating theater for many in the Defense Industrial…

Adam Sherer 1 May 2025 • 2 min read
cadencelive , defense

Time-of-Flight Decoding with Tensilica Vision DSPs

Today, let's break down time-of-flight (ToF) and how Tensilica Vision DSPs can be…

SriramK 29 Apr 2025 • 1 min read
IP , Consumer Electronics , cadence , video , Tensilica DSPs , ip cores , Tensilica , vision , semiconductor IP , cadencelive , imaging , image processing

Cadence San Jose Hosts JEDEC LPDDR Task Group Meeting

Low-power DDR ( LPDDR ) SDRAM has been one of the most widely used memories in the…

Shyam Sharma 24 Apr 2025 • 2 min read
Verification IP , Design IP , IP , VIP , JEDEC , LPDDR PHY IP , DRAM , LPDDR Controller IP , Design IP and Verification IP , Lpddr6

HBM4 Boosts Memory Performance for AI Training

The recent HBM4 specification announced by JEDEC is great news for developers of…

Frank Ferro 16 Apr 2025 • 2 min read
JEDEC , hbm4 , memory IP , AI training , data centers

Functional Safety in a Disaggregated World

We are witnessing a dramatic rise in disaggregation and a lot of discussion around…

MBhatnagar 9 Apr 2025 • 5 min read
Automotive , functional safety , fusa
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