Featured

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Arm Zena CSS – Accelerating Chiplet-Based SoC Design for AI-Defined Vehicles

Cadence is collaborating with Arm on their groundbreaking first-generation compute…

Robert
• 6 min read
virtual prototyping , ucie , featured , chiplet , virtual platform
SoC and IP

Latest blogs

Functional Safety in a Disaggregated World

We are witnessing a dramatic rise in disaggregation and a lot of discussion around…

• 5 min read
Automotive , functional safety , fusa

How Physical AI Is Redefining the Automotive Industry

The automotive world is experiencing a groundbreaking transformation, with technology…

• 5 min read
Automotive , IP , ev , physical ai , Software-Defined Vehicles , ADAS , AI

Cadence Silicon Success of UCIe IP on Samsung Foundry’s 5nm Automotive Process

We are thrilled to announce that Cadence has successfully demonstrated first-pass…

• 2 min read
ucie , PHY , samsung foundry

AI's Rapid Growth: The Crucial Role of High Bandwidth Memory

System efficiency is dictated by the performance of crucial components. For AI hardware…

• 5 min read
Design IP , IP , HBM

Symmetric Multiprocessing (SMP) RTOS on Xtensa Multicore

An increasing number of multi-threaded embedded applications want to leverage multicore…

• 8 min read
featured , Symmetric Multiprocessing , SMP , Tensilica , FreeRTOS , Xtensa , multicore , RTOS , multiprocessing

eUSB2 Version 2 with 4.8Gbps and the Use Cases: A Comprehensive Overview

When developing system-on-chip (SoC) solutions, the key features often minimize size…

• 3 min read
Design IP , cadence , PHY , USB-IF , USB , SoC , USB 2.0

Enkl Sound Elevates Audio Tech with Tensilica HiFi DSP for Unmatched Excellence

In the rapidly evolving world of audio technology, Enkl Sound Copenhagen emerges…

• 3 min read
Sound , Hearable , wearables , Tensilica HiFi DSP , Bluetooth Speakers

Accelerate the Photonic IC Design with Cadence EPDA Environment

Do you believe the existing semiconductor methodologies will adequately support the…

• 4 min read
Photonic IC Design , EPDA Environment , photonics

Accelerate Your Automotive, Consumer, and Data Center Semiconductor Projects

Semiconductor innovation is the driving force behind groundbreaking advancements…

• 3 min read
Automotive , featured , CES , Tensilica

Cadence Transforms Chiplet Technology with First Arm-Based System Chiplet

Cadence has achieved a significant milestone by designing and taping out its first…

• 4 min read
Automotive , ucie , featured , chiplets , NoC , lpddr5 , ARM

Simulating Multiple Cadence DSPs as Multiple x86 Processes

An increasing number of embedded designs are multi-core systems. At the pre-silicon…

• 4 min read
Tensilica , Xtensa , SystemC , multicore , simulation , multiprocessing

Redefining Hearing Aids with Cadence DSPs

Hearing is one of the most essential senses for engaging with the world. It enables…

• 4 min read
Tensilica DSPs , HiFi DSP , Fusion DSP Family , Hearing Aids

Driving Innovation: Cadence's Cutting-Edge IP on TSMC's N3 Node

Staying ahead of the curve is essential to meeting customer needs. Cadence has consistently…

• 2 min read
ucie , Memory , LPDDR , ip cores , PCIe , DDR , GDDR7

The Future of Driving: How Advanced DSP is Shaping Car Infotainment Systems

As vehicles transition into interconnected ecosystems, artificial intelligence and…

• 5 min read
Automotive , DSP , infotainment , Tensilica , HiFi 5s

Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem

Cadence tapes out 32G UCIe interface IP for high speed, highly efficient chiplet…

• 4 min read
ucie , IP , die-to-die

Locking When Emulating Xtensa LX Multi-Core on a Xilinx FPGA

Today's high-performance computing systems often require the designer to instantiate…

• 4 min read
AXI , Tensilica , Xtensa , FPGA

DDR5 12.8Gbps MRDIMM IP: Powering the Future of AI, HPC, and Data Centers

The demand for higher-performance computing is greater than ever. Cutting-edge applications…

• 2 min read
ddr5 , Design IP , IP , gddr6 , PHY , 3nm , MRDIMM , GDDR , memory IP , Denali , Design IP and Verification IP , DDR

GDDR7: The Ideal Memory Solution in AI Inference

The generative AI market is experiencing rapid growth, driven by the increasing parameter…

• 3 min read
featured , gddr6 , inference , HBM , training , AI , GDDR7

HBM3E: All About Bandwidth

The rapid rise in size and sophistication of AI/ML training models requires increasingly…

• 2 min read
featured , HBM , hbm4 , SerDes

How Cadence Is Revolutionizing Automotive Sensor Fusion

The automotive industry is currently on the cusp of a radical evolution, steering…

• 5 min read
Automotive , Sensor Processing , sensor fusion , Automotive SoC , automotive IP , NPU , AI

Are You SAFE Yet? Leveraging the Ecosystem to Boost Your Product Time to Market

We live in a rapidly growing “digitalized world,” with an ever-increasing need for…

• 2 min read
IP , featured , Silicon Solution Group , PCIe 5.0 , samsung foundry , PCIe , SSG , PCIe 6.0 , safe , PCI Express , Protocol IP

Navigating Chiplet-Based Automotive Electronics Design with Advanced Tools and F…

In the rapidly evolving landscape of automotive electronics, traditional monolithic…

• 6 min read
Automotive , electronics , chiplets , tools and flows

Cadence Showcases World's First 128GT/s PCIe 7.0 IP Over Optics

PCI-SIG DevCon 2024 was a great success for Cadence. We posted the blog, Cadence…

• 2 min read
Design IP , IP , featured , PHY , 128 GT/s , PCIe 7.0 , PCIe , Optics , SerDes , SerDes IP

How Cadence Is Expanding Innovation for 3D-IC Design

The market is trending towards integrating and stacking multiple chiplets into a…

• 5 min read

Cadence Demonstrates Complete PCIe 7.0 Solution at PCI-SIG DevCon ‘24

PCI-SIG DevCon 2024 – 32 nd Anniversary For more than a decade, Cadence has been…

• 6 min read
Design IP , IP , PHY , PCIe 7.0 , PCIe , semiconductor IP , SerDes , PCI Express , PCI-SIG

Chiplet Integration in the Automotive Realm

As technology continues to advance, the automotive industry is rapidly transforming…

• 4 min read
Automotive , ucie , chiplets , 3D-IC , design flow , d2d , verification

Cadence San Jose Hosts JEDEC LPDDR (Low-Power DDR) Task Group Meeting

Low-power DDR (LPDDR ) SDRAM has been one of the most widely used memories in the…

• 1 min read
Verification IP , ddr5 , IP , JEDEC , HBM , GDDR , memory IP , DRAM , lpddr5 , lpddr5x , memory models

UCIe and Automotive Electronics: Pioneering the Chiplet Revolution

The automotive industry stands at the brink of a profound transformation fueled by…

• 5 min read
ucie , IP , ip cores , Tensilica
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