Cadence San Jose Hosts JEDEC LPDDR Task Group Meeting

Low-power DDR (LPDDR) SDRAM has been one of the most widely used memories in the semiconductor market today. It’s used in a diverse set of applications that spans mobile/handheld devices, IoT, client and server, automotive, Virtual Reality/gaming consoles, robotics, data centers, and AI applications, just to name a few.

On April 9 and 10, 2025, Cadence San Jose hosted the JEDEC LPDDR Task Group face-to-face meeting, which is designated to define the memory standard for the next generation of low-power DDR memories. This is the fourth year in a row that Cadence has hosted the JEDEC LPDDR Task Group meeting, with Cadence being the venue for similar face-to-face meetings in 2024, 2023, and 2022. 

Here is some background on JEDEC. For over 50 years, JEDEC has been the global leader in developing open standards for the microelectronics industry, and the JEDEC membership includes industry-leading semiconductor companies.

LPDDR6 is a next-generation low-power memory standard that is expected to support:

• Increasing bandwidth: To support Al applications and HPC use cases, various high-frequency enablers are being considered.
• Lowering power usage: LPDDR6 will continue to reduce power as compared to the prior version of the standard.
• Enhanced RAS (Reliability, Availability and Serviceability) to improve security and performance.

The meeting was well attended, with more than 50 members from 20+ companies joining the meeting in person and remotely with in-person meeting participants, including people from some of the most important semiconductor companies in the world.

This face-to-face meeting enabled leaders who are part of JEDEC LPDDR TG to make significant progress on the next-generation LPDDR standard.

“The JEDEC LPDDR Task Group face-to-face meeting is a significant step in defining the future Low-Power DRAM industry standards like Lpddr6 for next-generation applications,” said Osamu Nagashima of Advantest and chair of the JEDEC LPDDR committee. “Cadence, being a valued task group member, has graciously hosted this meeting annually for the last 4 years.”

Cadence memory IP system solutions offer world-class LPDDR, DDR, GDDR, and HBM PHY and controller IP that are flexible and configurable to support a wide range of applications.

Cadence verification IPs offer a compressive memory subsystem solution that includes a memory model for LPDDR5 and LPDDR5X, DFI memory controller/PHY VIPs, and a system VIP compliant to JEDEC spec-defined LPDDR5/LPDDR5X feature set along with latest DFI specification.

Cadence IP and VIP are expected to support next-generation LPDDR memory-standard LPDDR6, tracking JEDEC standard.

If you have any queries, feel free to contact us at talk_to_vip_expert@cadence.com

More information on Cadence LPDDR5/LPDDR5X VIP is available at Cadence VIP Memory Models Website.