CadenceLIVE 2025: The Field Guide for Defense Digital Engineering

1 May 2025 • 2 minute read

Modern microelectronics is a new operating theater for many in the Defense Industrial Base (DIB). It’s no longer a question of if but how to modernize. CadenceLIVE is replete with technical papers and keynote vision that form the field guide the DIB needs to move forward boldly.

While the full agenda has many worthy technical papers, I’ve used my experience as a principal investigator on multiple Defense programs to assemble this handy field guide to CadenceLIVE 2025.

0800 – 0900: Register, network, and carbo-load. It’s going to be a high-energy day.

0900 – 1100: Can’t-miss keynotes!

Fireside chat with NVIDIA CEO Jensen Huang and Cadence president and CEO Anirudh Devgan
Keynotes from Cadence’s CEO, Anirudh Devgan, and Google AI’s Uri Frank. Expect to hear unique insights into how AI is transforming electronics development and more.

1115 – 1145:

(Room M3) Raytheon: How Stratus high level synthesis is speeding algorithmic development of FPGA and ASIC systems for the DoD
(Room 212) Secure-IC: How trust can be assured in chiplet-based design

1145 – 1215:

(Room M3) GlobalFoundries: Optimizing aging effects using Liberate and Tempus in an advanced aging flow
(Room G) Boeing: Applying multi-physics analysis for validating and mitigating thermal effects in PCB design
(Room 210) AFRL: Applying digital engineering to microelectronics designs

1215 – 1345: Lunch and chase speakers, sponsors, and peers for 1:1 discussions. Start with “Tell me about your technology.” That’s the #1 best ice breaker with engineers. The carbs from the morning will help you keep up once they get going.

1345 – 1415:

(Room M3) JPO: Bridging the Abstraction Chasm from MBSE to implementation (I’m a co-author!)
(Room Great America 3) Intel: Applying Cerebrus AI to enhance power performance and area (PPA)

1415 – 1445:

(Room B4) Cadence: System design and use cases of AI-driven DSP technologies
(Room M4) Cycuity+ADI: Assuring comprehensive functional and security coverage (I’m a co-author for this one, too!)
(Room 210) ADI: Pre-silicon power estimation and profiling using Palladium Dynamic Power Analysis

1445 – 1515:

(Room 204) InPlay: RF/AMS foundry porting and optimization for modernization
(Room 205) GlobalFoundries: 45SPCLO silicon photonics reference flow for 4x4 optical switch
(Room G) Teradyne: Revolutionizing signal integrity optimization with AI/ML technology for high-speed channel breakout

1515 – 1600: Relax, network, recharge, and get ready for…

1600 – 1630: Another can’t miss fireside chat!

Intel CEO Lip Bu Tan and Cadence president and CEO Anirudh Devgan

1645 – 1715:

(Room 204) NASA JPL: Co-sim of polar and mid-latitude Mars subsurface ice and ultra-wideband Radar for the Mars Science Helicopter (if you want to find me at 1645, this is where I’ll be #spacegeek)
(Room 207) Celus: Translating ideas into complete BOMs and outputs with AI (could help where we have incomplete technical data packages – TDPs)

1715 – 1745:

(Room B4) TI: Midas Safety Platform enables FMEDA automation throughout functional safety lifecycle
(Room 210) Cadence: Broadening adoption of HW-assisted verification with next-generation emulation appliance (stay for this one, it will be interesting!)

1800 - 1900:

Join us for the evening reception, presentation awards ceremony, and design expo!

My recommendation is to plan ahead because this CadenceLIVE has a great set of technical briefs for Defense attendees. I’m looking forward to seeing you all there!