Featured

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Arm Zena CSS – Accelerating Chiplet-Based SoC Design for AI-Defined Vehicles

Cadence is collaborating with Arm on their groundbreaking first-generation compute…

Robert
• 6 min read
virtual prototyping , ucie , featured , chiplet , virtual platform
SoC and IP

Latest blogs

Celebrating World Intellectual Property Day

LEGO ® is the world’s most famous toy brand. The experience of playing with these…

• 1 min read
Design IP , IP

Intel and Cadence Partner to Build Out the Foundry Ecosystem in America

As a result of the largest public-private investment ever made in the U.S. semiconductor…

• 3 min read
CXL , IP , featured , PCIe 5.0 , PCIe , CHIPS and Science Act , Silicon Solutions Group , Intel Foundry

Revolution on the Road: How Cadence is Driving the Future of Automotive Design!

The automotive industry is at a crucial inflection point, pivoting from traditional…

• 8 min read
functional safety , Automotive Solutions , infotainment , autonomous driving , Automotive Ethernet , automotive IP , ADAS

Cadence Sets the Gold Standard for UCIe Connectivity at Chiplet Summit '24

Cadence Demonstrated first silicon in UCIe during Chiplet Summit 2024. The demo showed…

• 3 min read
ucie , UltraLink , IP , die-to-die , d2d

UCIe Interoperability Between Intel and Cadence

Intel and Cadence are collaborating on an initiative to demonstrate interoperability…

• 3 min read
ucie , chiplets , IP integration , semiconductor IP , Design IP and Verification IP

Cadence is a Contributing UCIe Consortium Member

This blog was originally posted on uciexpress.org . The Cadence member spotlight…

• 5 min read
ucie , chiplets , Design IP and Verification IP

Cadence Targets Automotive Market Demands with UCIe

Cadence has become a contributor-level member of the Automotive Working Group in…

• 2 min read
ucie , IP , chiplets , Design IP and Verification IP

How Do Robots Navigate?

Have you ever been amazed by the graceful movement of robots and self-driving vehicles…

• 4 min read
ip cores , Tensilica , VSLAM

Cadence Perspective: 224G SerDes Trend and Solution

As an industry early mover to support the emerging 800G/1.6T networks, Cadence taped…

• 4 min read
LLM

Cadence Showcases PCIe 7.0-Ready IP at PCI-SIG Developers Conference 2023

PCIe 7.0 continues to progress through draft stage, IP enablement begins The PCI…

• 2 min read
Design IP , IP , PHY , semiconductor IP , SerDes , PCI Express , PCI-SIG

Cadence Collaboration with Kudan and Visionary.ai Enables Rapid Deployment of VSLAM…

Are you confused while navigating new environments, especially in less optimum light…

• 5 min read
Visionary.ai , SLAM , Tensilica , vision , Kudan

Cadence Demonstrates 112G-ELR SerDes IP on TSMC’s 3nm Process Technology

The 3nm wave of technology is here! Cadence is proud to demonstrate its 112G Extended…

• 2 min read
featured , 112g , SerDes IP

The Five Must-Have Features of Modern Automotive SoC Architectures

Groundbreaking innovations demand state-of-the-art system-on-chip (SoC) architectures…

• 3 min read
security , Automotive , Low Power , featured , Safety , system-on-chip , predictability , real-time processor , architectures , high performance , connectivity

FMEDA-Driven SoC Design of Safety-Critical Semiconductors

Written by Francesco Lertora and Robert Schweiger 1.1 Introduction The growing…

• 8 min read
Safety Solution , Genus , functional safety , Midas Safety Platform , featured , Xcelium Safety , Jasper FSV , Verisium Manager Safety , USF , Automotive Option , Safety Analysis , Innovus , FMEDA , ISO 26262 , Virtuoso Assembler , Unified Safety Format , Safety Verification , Safety Compliance , Legato Reliability , Safety-aware Implementation

Building Robust PCI Express IP Solutions: Compliance and Beyond

Discover PCIe Going from draft specification to being listed as compliant on the…

• 3 min read
featured , PCIe , PCI Express

AI in Healthcare

Artificial Intelligence and edge computing are revolutionizing the healthcare industry…

• 4 min read
artificial intelligence , featured , Edge Computing , healthcare , AI

TWS Earbud Design: Scaling up

We now look to scale the architecture from Good-enough earbuds, to Better (mid-tier…

• 9 min read
Tensilica DSPs , Tensilica

TWS Earbud Design Is About Scaling

It is important that OEMs and SoC providers of TWS earbuds prepare to offer the quality…

• 5 min read
featured , Tensilica

Leveraging Vision for Depth Perception in Autonomous Driving

The automotive industry is inching towards enhancing the driver’s experience and…

• 6 min read
autonomous driving , depth , Tensilica , iso26262 , ADAS , fusa

High-Speed 112G Design and COM Dependencies

The design impairments such as SoC packaging, package-to-board impedance mismatch…

• 5 min read
high-speed , 112g , SerDes , SerDes IP , COM Dependencies , Log-Reach

Improving Performance and Throughput While Implementing FFT Using Tensilica ConnXB20…

Real-time FFT performance in Radar, Lidar, and ADAS applications is limited by data…

• 6 min read
DSP , cadence , tie , semiconductor IP , DIT , Tensilica IP , FFT

PCIe for Automotive - DesignCon/DriveWorld 2021

DesignCon 2021, Drive World Conference, and Embedded Systems Conference are a joint…

• 3 min read
CXL , Design IP , IP , featured , PCIe Gen4 , ip cores , PCI , PCIe PHY

Introducing Cadence IP for PCIe 6.0

Since its inception, PCI Express® (PCIe®) has proliferated quickly to become ubiquitous…

• 3 min read
controller IP , CXL , Design IP , IP , PHY , PCIe , semiconductor IP , SerDes , PCIe 6.0 , PCI Express

First Look: Cadence Subsystem SoC for PCIe 5.0

If a picture is worth a thousand words, a video tells you the entire story. Cadence…

• 1 min read
controller IP , CXL , PCI Express 5.0 , Design IP , IP , PHY , Gen5 , PCIe , semiconductor IP , Design and Verification IP , SerDes , Compute Express Link , SerDes IP , PCI Express

Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0

Cadence was the first IP provider to bring controllers for PCI Express (PCIe) 3.0…

• 2 min read
controller IP , CXL , PCI Express 5.0 , Design IP , IP , PHY , Gen5 , PCIe , semiconductor IP , Design IP and Verification IP , SerDes , Compute Express Link , SerDes IP , PCI , PCI Express

PCI-SIG DevCon 2019 APAC Tour: All Around Latest Spec Updates and Solution Offer…

PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus is…

• 2 min read
PCI Developers Conference , Design IP , PCIe Gen4 , PCIe Gen3 , PCIe PHY , PCIe Gen5 , PCI Express , PCI-SIG

Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product

The PCI-SIG finalized the PCIe 4.0 specification with doubling the data to 16GT/s…

• 2 min read
PCIe controller , Design IP , IP , PCIe Gen4 , PHY , IP design , PCIe , semiconductor IP , SerDes , PCIe PHY , PCI Express

PCIe 3.0 Still Shines While PCIe Keeps Evolving

PCIe has been widely adopted in the electronics industry since its first debut in…

• 2 min read
USB 3.0 , Design IP , IP , USB Type-C , DisplayPort , PCIe , PCIe Gen3 , SerDes , USB 3.1
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