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Discover PCIeGoing from draft specification to being listed as compliant on the integrators list by PCI-SIG is a multiple-year journey. The preliminary PCIe® 5.0 specification was announced in June 2017, with the final specification released in May 2019 and the first official compliance workshop conducted in April 2022. This represents the complexity of the products being built and the ecosystem required to support them.
Cadence has been a longstanding member of the PCI-SIG and an active developer of PCIe IP. With multiple compliant products listed on the integrators list, PCIe 5.0 was no exception. We built on our prior expertise to enhance our subsystem solutions to develop IP that meets these rigorous specifications while participating in the collaborative compliance program.
PCI-SIG Compliance Program: PCIe 5.0The Serial Enabling Workgroup (SEG) runs the PCI-SIG compliance program. The compliance program intends to ensure that devices that are certified to be compliant will interoperate together. The compliance program includes a set of electrical and protocol compliance tests against which devices need to pass, with specified test procedures at PCI-SIG organized workshops. In addition, at these workshops, PCI-SIG members are required to test their devices against other members’ products for interoperability.The SEG works with member companies and test equipment vendors while developing the test programs for each version of the specification. The program covers various areas of the specification.
For PCIe 5.0, prior to the official compliance workshops held in April 2022, the PCI-SIG conducted “FYI” workshops for over a year through 2021. These FYI workshops were more than a dry run. They served an important purpose in refining test procedures and ensuring that equipment and software operated reliably. The confidential nature of these workshops allowed competitors to collaborate and improve their own products and the standard—true co-opetition that moves the industry forward!
Cadence built on its prior successes with 3.0 and 4.0 compliance with a unique approach to PCIe 5.0. By building an IP subsystem in silicon, we could test the entire protocol stack as an 8-lane solution that encompasses many of the applications our customers use in practice.
PCIe 5.0 subsystem daughter card
PCIe 5.0 subsystem block diagram
The Cadence PCIe 5.0 products performed well throughout the FYI program and achieved compliance at the first workshop in April 2022. With limited test spots available, we certified our endpoint products in multiple process nodes at this event. Our root port configurations were certified in the July 25 – 28 workshop and will appear on the integrators list shortly.
Cadence PCIe 5.0 under test at the compliance workshop in April 2022
While compliance testing examines a necessary set of requirements for products to be interoperable, in real life, these are a basic minimum set of tests that products need to meet.In real systems, we encounter scenarios that test corner conditions with link errors, speed changes, and power state changes. Our labs are set up to stress test these conditions, with these events occurring hundreds of thousands of times over various temperature and process conditions on a wide range of commercially available platforms. In addition to the 8-lane add-in cards, we have also built U.2 form factor cards that can be easily plugged into rack-mounted systems for this purpose. By exhaustively testing under these conditions, we can assure the adopters of our IP solutions that their applications will perform robustly.
Visit our PCIe 5.0 technology page for the latest news on this technology from Cadence.Discover PCIe