The Power of Shifting Left: Cadence Accelerating Innovation with Arm

7 Nov 2025 • 3 minute read

In semiconductor design, projects are remembered for their extremes—legendary successes and cautionary failures. The difference often hinges on when problems are discovered. A bug found late in development can derail timelines and budgets. This is why "shifting left"—moving testing and validation earlier in the process—is now a critical strategy for innovation.

Why Shifting Left Matters

Shifting left means bringing testing, verification, and validation activities forward in the design cycle. Instead of waiting for physical prototypes, teams use simulation and emulation to catch issues early. This proactive approach reduces costs, accelerates time to market, and minimizes the risk of late-stage surprises. The cost delta is staggering. NASA's research shows that the cost of fixing a bug multiplies tenfold at each stage of development. A bug caught during requirements costs "1X"; during design, "10X"; during build, "100X"; and in production, "1000X." That is real money, real time, and real risk.

Cadence's Approach to IP Integration

At Cadence, we've made shifting left a core part of our IP delivery model. Take PCI Express^® (PCIe^®) technology: previously, customers received separate controller and PHY components and were left to sort out integration challenges themselves. We changed that by delivering pre-verified subsystems—controller and PHY tested together in real environments. We own the integration risk, not our customers. We apply this industry standard to emerging technologies such as CXL^™ and UCIe^™.

Arm Neoverse CSS Ecosystem: Blueprint for Acceleration

Arm^® Neoverse^® Compute Subsystems (CSS) take this approach further. Going beyond discreet IP, Arm delivers a pre-integrated, pre-verified platform—cores, mesh, and control logic, all ready to go. The Server Base System Architecture (SPSA) and SystemReady compliance suite mean hardware boots "out of the box." This robust framework eliminates bottlenecks and accelerates system bring-up.

Cadence + Arm: Multi-Platform Validation for Real-World Success

As a key Arm partner, we provide next-generation IP for interfaces such as PCIe, CXL, and DDR memory. Our multi-platform validation pipeline embodies shift-left as follows:

RTL Simulation with Xcelium Logic Simulation: Early sanity checks catch fundamental issues in PCIe transactions and memory operations.
Emulation with Palladium Solution: High-speed, hardware-based emulation runs full Arm SystemReady validation suites, stress-testing systems before silicon exists.
Full Compliance Testing: Rigorous multi-stage testing ensures our IP meets SPSA and SystemReady specifications, giving customers confidence from day one.

What truly sets this collaboration apart is the depth and breadth of our validation strategy. By leveraging both simulation and emulation, we replicate real-world scenarios and workloads, uncovering edge cases that might otherwise go undetected until late in the development cycle. This means our customers receive IP that's not only functionally robust but also proven to perform under demanding conditions.

Our teams work closely with Arm engineers to co-develop test plans, share insights, and rapidly iterate on solutions. This joint effort accelerates the identification and resolution of integration challenges, ensuring that our IP seamlessly fits within the Arm Neoverse CSS ecosystem. We also validate across multiple platforms and configurations, from basic boot sequences to complex memory and connectivity operations, so customers can trust that their systems will work as intended, right out of the box.

Some interfaces, such as PCIe and DDR5, require special attention due to legacy quirks and boot requirements. Cadence integrates and validates these within Arm Neoverse CSS environments, ensuring robust, low-risk solutions for customers. This comprehensive, collaborative approach is the foundation for delivering innovation at speed and scale.

The Future: Collaborative, Accelerated Innovation

The ongoing collaboration between Cadence and Arm is continually evolving. As new Arm Neoverse CSS versions and protocol standards emerge, we co-validate solutions to stay ahead. Test chips featuring Cadence IP and Arm cores validate functionality in silicon, shifting left before customers even start their designs.

Whether through leading-edge IP, full subsystem integration, or cloud-based validation, Cadence is committed to customer success. By embracing shift-left and collaborating with Arm, we're building not just better components, but a faster, more efficient path to innovation.