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Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G
• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar
• 3 min read
ucie , Design IP , featured , TSMC , die-to-die

Arm Zena CSS – Accelerating Chiplet-Based SoC Design for AI-Defined Vehicles

Cadence is collaborating with Arm on their groundbreaking first-generation compute…

Robert
• 6 min read
virtual prototyping , ucie , featured , chiplet , virtual platform
SoC and IP

Latest blogs

Is the Role of Test Chips Changing at Advanced Foundry Nodes?

Test chips are becoming more widespread and more complex at advanced process nodes…

• 3 min read
Design IP , IP , cadence , PCIe Gen4 , IP integration , ip cores , Ethernet , semiconductor IP , PCI Express

SemiEngineering Article: Why IP Quality Is So Difficult to Determine

Differentiating good IP from mediocre or bad IP is getting more difficult, in part…

• 3 min read
IP , cadence , IP blocks , Automotive Ethernet , ip cores , Tensilica , semiconductor IP , Design IP and Verification IP

Designing for the Future - Managing the Impact of Moore's Law

With Moore’s Law, the industry assumes that when you go from one geometry to the…

• 3 min read
Design IP , IP , LPDDR , PCIe Gen4 , MIPI , USB , SerDes

NXP Introduces Tensilica HiFi 4 DSP-based Platforms to Secure IoT Edge Devices

Trust. Privacy. Confidentiality. These are three important concerns for designers…

• 1 min read
IP , IoT , HiFi , ip cores , Tensilica , semiconductor IP , Internet of Things

Cadence Tensilica Fusion F1 DSP Stars in NB IoT Applications

Did you make it to MWC Shanghai? I didn’t, but I read about what was hot – narrowband…

• 1 min read
DSP , IoT , Fusion , ip cores , Tensilica , nb-iot

Chip Dis-integration

I was asked the following question recently. No longer are we seeing increasing…

• 5 min read
chiplets , IoT , Design IP and Verification IP , moore's law , 2.5D interposer

Why Software-Based GPS Is Great for Location-Based IoT Applications

At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo…

• 1 min read

Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would…

• 4 min read
Galileo , GPS , IoT , Tensilica DSPs

See You in Barcelona at MWC!

I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never…

• 1 min read
DSP , IP , Mobile World Congress , ip cores , Tensilica , vision , imaging

What I Learned About System Design Enablement at DesignCon

While attending the recent DesignCon show for the first time, I was struck by the…

• 2 min read
IP , IP integration , SDE , Sigrity , system design enablement

A Walk Through DesignCon Turns Into a Long Journey

Have you ever attended the DesignCon show? I attended the recent event for the first…

• 2 min read
IP , IP integration , SDE , noise , Sigrity

You Won't Believe Your Ears When Listening to Your Laptop

I wouldn't believe it if I hadn't heard it myself on a laptop in the Cadence booth…

• 2 min read
CES , audio , HiFi , Tensilica

Book Your CES Meetings Now!

Want to see the exciting technology that is behind some of the biggest innovations…

• 1 min read

USB 3.2—The USB Type-C Connector Finally Met its Match

It’s only a week before the first event of USB Developer Days , a series of meetings…

• 1 min read
USB 3.0 , USB Type-C , DisplayPort , USB , USB 3.2 , power delivery , USB 3.1

Cadence IP Is Great for Automotive

If you’re designing chips for in-vehicle infotainment, in-cabin electronics, vision…

• less than a min read
USB 3.0 , Design IP , DDR4 , LPDDR4 , PCI Express 3.0 , LPDDR , IP blocks , PCIe Gen4 , MIPI , DisplayPort , Automotive Ethernet , USB , memory IP , Ethernet , PCIe , 16nm , PCIe Gen3 , imaging , Ethernet PHYs , PCI

What’s New With Cadence PCI Express IP? Almost Everything!

PCI-SIG Developer’s Conference 2017 was held in Santa Clara, California in June this…

• 1 min read
IP , TSMC , Gen4 , PCIe , 16nm , PCI Express 4.0 , 7nm , PCI-SIG

It's a Visual World

Here’s an experiment to try: in a quiet (but crowded) Auditorium, drop a stack of…

FormerMember • 7 min read
controller IP , Design IP , IP , IP blocks , Embedded Vision Summit , vision processing , Jitendra Malik , IP design , Tensilica , vision , future of IP , Design IP and Verification IP , imaging , image processing

Happy Birthday Tensilica

Yes, it’s Tensilica’s birthday! Twenty years ago today, on July 31, 1997, Tensilica…

• 2 min read
DSP , Chris Rowen , HiFi , Tensilica , vision

What Will It Take to Bring DNN to Embedded?

If you missed Michelle Mao’s presentation at the recent Autosens conference in Detroit…

• less than a min read
architecture , Vision C5 , Tensilica , vision , dnn , CNN , neural nets , embedded

USB Type-C: Let’s Get Real

Have you tried a product incorporating the new USB Type-C port? Do you wonder how…

• 1 min read
Design IP , USB Type-C , USB-IF , USB , Type-C , Design IP and Verification IP , USB 3.1

Memory Trends for Automotive Markets

Remember automobiles from a few years ago? They were pretty simple machines with…

• 4 min read
Design IP , IP , Memory , LPDDR4 , LPDDR , DIP , memory IP , Design IP and Verification IP , memories

Three New Memory Trends in Enterprise Data Centers

You might have seen the graph below about the increase in monthly internet traffic…

• 5 min read
Design IP , Memory , DDR4 , flash , memory IP , DDR , memories

3 Reasons That the Semiconductor Clouds Are Gathering

With cloud technology going vertical, everything is changing. The world is connected…

• 3 min read
CDNLive , PCIe Gen4 , virtual reality , augmented reality

3 Things You Didn't Know About MemCon 2016

Memcon is an event like few others, where SoC architects congregate to learn and…

• 1 min read
DDR4 , LPDDR4 , MemCon , DDR IP

HoloLens Is at the Tip of the Tensilica Iceberg, With Processors That Scale to Any…

Microsoft provided details of their HoloLens HPU at HotChips this week, revealing…

• less than a min read
IP , controller , Tensilica , augmented reality

MIPI DevCon 2016 – Mobile and Beyond

MIPI DevCon 2016 – Mobile and Beyond The word “beyond” may bring up thoughts of…

• 6 min read
MIPI Alliance , ADAS

Less is More With MIPI I3C

There is little doubt that Internet of Things has become the next big thing in business…

• 1 min read
peripherals , IoT , MIPI , i2c , sensors , hdr , I3C , sensewire , hub

Building the Cars of the Future

The big buzz in the automotive industry lately is autonomous driving vehicles. Companies…

• 3 min read
Verification IP , VIP , Automotive Ethernet , CAN , automotive electronics , Ethernet , Design IP and Verification IP , Lin
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