SoC and IP - Cadence Blogs - Cadence Community

Blogs
SoC and IP

SoC and IP Blogs

Never miss a story from SoC and IP. Subscribe for in-depth analysis and articles.

Subscribe by email
More
Cancel

Search

This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

Featured

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

Arif Khan 7 Nov 2025 • 3 min read

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

Sheryl G 7 Oct 2025 • 3 min read

Design IP , featured , 224G-LR , 224G SerDes , UALink

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

MBhatnagar 22 Sep 2025 • 3 min read

ucie , Design IP , featured , TSMC , die-to-die

SoC and IP

Latest blogs

Taking the Wraps Off: Cadence IP Subsystem for PCIe 5.0

Cadence was the first IP provider to bring controllers for PCI Express (PCIe) 3.0…

Arif Khan 12 Apr 2021 • 2 min read

controller IP , CXL , PCI Express 5.0 , Design IP , IP , PHY , Gen5 , PCIe , semiconductor IP , Design IP and Verification IP , SerDes , Compute Express Link , SerDes IP , PCI , PCI Express

PCI-SIG DevCon 2019 APAC Tour: All Around Latest Spec Updates and Solution Offer…

PCI-SIG DevCon 2019 APAC tour has come to Tokyo and Taipei this year. The focus is…

William Chen 29 Oct 2019 • 2 min read

PCI Developers Conference , Design IP , PCIe Gen4 , PCIe Gen3 , PCIe PHY , PCIe Gen5 , PCI Express , PCI-SIG

Did You “Stress Test” Yet? Essential Step to Ensure a Quality PCIe 4.0 Product

The PCI-SIG finalized the PCIe 4.0 specification with doubling the data to 16GT/s…

William Chen 17 Oct 2019 • 2 min read

PCIe controller , Design IP , IP , PCIe Gen4 , PHY , IP design , PCIe , semiconductor IP , SerDes , PCIe PHY , PCI Express

PCIe 3.0 Still Shines While PCIe Keeps Evolving

PCIe has been widely adopted in the electronics industry since its first debut in…

William Chen 15 Oct 2019 • 2 min read

USB 3.0 , Design IP , IP , USB Type-C , DisplayPort , PCIe , PCIe Gen3 , SerDes , USB 3.1

Is the Role of Test Chips Changing at Advanced Foundry Nodes?

Test chips are becoming more widespread and more complex at advanced process nodes…

TomWong 15 Jul 2019 • 3 min read

Design IP , IP , cadence , PCIe Gen4 , IP integration , ip cores , Ethernet , semiconductor IP , PCI Express

SemiEngineering Article: Why IP Quality Is So Difficult to Determine

Differentiating good IP from mediocre or bad IP is getting more difficult, in part…

TomWong 7 Jun 2019 • 3 min read

IP , cadence , IP blocks , Automotive Ethernet , ip cores , Tensilica , semiconductor IP , Design IP and Verification IP

Designing for the Future - Managing the Impact of Moore's Law

With Moore’s Law, the industry assumes that when you go from one geometry to the…

TomWong 15 May 2019 • 3 min read

Design IP , IP , LPDDR , PCIe Gen4 , MIPI , USB , SerDes

NXP Introduces Tensilica HiFi 4 DSP-based Platforms to Secure IoT Edge Devices

Trust. Privacy. Confidentiality. These are three important concerns for designers…

PaulaJones 10 Oct 2018 • 1 min read

IP , IoT , HiFi , ip cores , Tensilica , semiconductor IP , Internet of Things

Cadence Tensilica Fusion F1 DSP Stars in NB IoT Applications

Did you make it to MWC Shanghai? I didn’t, but I read about what was hot – narrowband…

PaulaJones 2 Jul 2018 • 1 min read

DSP , IoT , Fusion , ip cores , Tensilica , nb-iot

Chip Dis-integration

I was asked the following question recently. No longer are we seeing increasing…

TomWong 27 Jun 2018 • 5 min read

chiplets , IoT , Design IP and Verification IP , moore's law , 2.5D interposer

Why Software-Based GPS Is Great for Location-Based IoT Applications

At the Cadence booth at Mobile World Congress in Barcelona, we’re featuring a demo…

PaulaJones 27 Feb 2018 • 1 min read

Delivering on the IoT Promise with Galileo Software GPS and Tensilica DSP IP

What is a software GPS, what does it have to do with Tensilica DSP IP, and why would…

tomhackett 23 Feb 2018 • 4 min read

Galileo , GPS , IoT , Tensilica DSPs

See You in Barcelona at MWC!

I’ve been going to Mobile World Congress in Barcelona for over 10 years, and it never…

PaulaJones 12 Feb 2018 • 1 min read

DSP , IP , Mobile World Congress , ip cores , Tensilica , vision , imaging

What I Learned About System Design Enablement at DesignCon

While attending the recent DesignCon show for the first time, I was struck by the…

tomhackett 9 Feb 2018 • 2 min read

IP , IP integration , SDE , Sigrity , system design enablement

A Walk Through DesignCon Turns Into a Long Journey

Have you ever attended the DesignCon show? I attended the recent event for the first…

tomhackett 9 Feb 2018 • 2 min read

IP , IP integration , SDE , noise , Sigrity

You Won't Believe Your Ears When Listening to Your Laptop

I wouldn't believe it if I hadn't heard it myself on a laptop in the Cadence booth…

PaulaJones 31 Jan 2018 • 2 min read

CES , audio , HiFi , Tensilica

Book Your CES Meetings Now!

Want to see the exciting technology that is behind some of the biggest innovations…

PaulaJones 4 Dec 2017 • 1 min read

USB 3.2—The USB Type-C Connector Finally Met its Match

It’s only a week before the first event of USB Developer Days , a series of meetings…

Jacek Duda 19 Sep 2017 • 1 min read

USB 3.0 , USB Type-C , DisplayPort , USB , USB 3.2 , power delivery , USB 3.1

Cadence IP Is Great for Automotive

If you’re designing chips for in-vehicle infotainment, in-cabin electronics, vision…

PaulaJones 12 Sep 2017 • less than a min read

USB 3.0 , Design IP , DDR4 , LPDDR4 , PCI Express 3.0 , LPDDR , IP blocks , PCIe Gen4 , MIPI , DisplayPort , Automotive Ethernet , USB , memory IP , Ethernet , PCIe , 16nm , PCIe Gen3 , imaging , Ethernet PHYs , PCI

What’s New With Cadence PCI Express IP? Almost Everything!

PCI-SIG Developer’s Conference 2017 was held in Santa Clara, California in June this…

Sachin Dhingra 22 Aug 2017 • 1 min read

IP , TSMC , Gen4 , PCIe , 16nm , PCI Express 4.0 , 7nm , PCI-SIG

It's a Visual World

Here’s an experiment to try: in a quiet (but crowded) Auditorium, drop a stack of…

FormerMember 22 Aug 2017 • 7 min read

controller IP , Design IP , IP , IP blocks , Embedded Vision Summit , vision processing , Jitendra Malik , IP design , Tensilica , vision , future of IP , Design IP and Verification IP , imaging , image processing