Never miss a story from SoC and IP. Subscribe for in-depth analysis and articles.
The 3nm wave of technology is here! Cadence is proud to demonstrate its 112G Extended Long-Reach (112G-ELR) SerDes IP on TSMC’s 3nm (N3E) process technology at the TSMC 2023 North America Technology Symposium this week. This is the latest addition to the Cadence 112G-ELR SerDes IP family. Riding the wave of More than Moore, FinFET transistors keep shrinking in TSMC’s 3nm process as they move towards system-in-package (SiP) designs. Combining the benefits of process technology advancement and Cadence’s best-in-class digital signal processor (DSP)-based SerDes architecture, the new 112G-ELR SerDes IP supports insertion loss (IL) of 45dB with exceptional power, performance, and area (PPA), making it ideal for hyperscale ASICs, artificial intelligence/machine learning (AI/ML) accelerators, switch fabric system-on-chips (SoCs) and 5G infrastructure applications.
Eye diagram of Cadence’s 112G-ELR SerDes on TSMC’s 3nm process (@ 106.25Gbps PAM4)
The ELR SerDes PHY is compliant with IEEE and OIF Long-Reach (LR) standards while providing additional performance margin beyond the standard specifications. The eye diagram above shows three wide-open eyes with good symmetry separating the four signal levels in PAM4 mode. The 3nm demonstration shows exceptional bit error rate (BER) performance of E-10 level with a channel of 39dB bump-to-bump IL, providing ample performance margin compared to the standard specification of less than 1E-4 at 28dB ball-to-ball IL.
Demo board and setup of Cadence’s 112G-ELR SerDes on TSMC’s 3nm process
The 112G-ELR SerDes IP also supports Medium Reach (MR) and Very Short Reach (VSR) applications with a flexible power-saving capability over different channels. The supported data rates range from 1G to 112G with NRZ and PAM4 signaling, enabling reliable high-speed data transfer over backplane, direct-attached cable (DAC), chip-to-chip and chip-to-module channels.
The SerDes IP incorporates an advanced DSP-based architecture with maximum likelihood sequence detection (MLSD) and reflection cancellation technologies that enable system robustness for lossy and reflective channels. MLSD is a powerful technique to improve BER and provides improved burst-error handling capability. Through proprietary implementation techniques, Cadence ensures that the power overhead of MLSD is minimal. The reflection cancellation technique cancels spurious, far-out reflections in a product environment with practical traces and connectors and thus provides robustness in BER outcomes.
Cadence’s 112G-ELR SerDes solution on TSMC’s 3nm process further solidifies our leadership position with high-performance connectivity IP offerings for hyperscale data centers, and customers can also enjoy the significant power and performance benefits associated with the TSMC 3nm process technology, the most advanced technology in both PPA and transistor technology.
For more information on the 112G-ELR SerDes, please visit www.cadence.com/go/112Gblog.