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Test chips are becoming more widespread and more complex at advanced process nodes as design teams utilize early silicon to diagnose problems prior to production. But this approach also is spurring questions about whether this approach is viable at 7nm and 5nm, due to the rising cost of prototyping advanced technology, such as mask tooling and wafer costs.
Semiconductor designers have long been making test chips to validate test structures, memory bit cells, larger memory blocks, and precision analog circuits like current mirrors, PLLs, temperature sensors, and high-speed I/Os. This has been done at 90nm, 65nm, 40nm, 32nm, 28nm, etc., so having test chips at 16nm, 7nm, or finer geometries should not be a surprise. Still, as costs rise, there is debate about whether those chips are over-used given advancements in tooling, or whether they should be utilized even more, with more advanced diagnostics built into them.
Modern EDA tools are very good. You can simulate and validate almost anything with certain degree of accuracy and correctness. The key to having good and accurate tools and accurate results (for simulation) is the quality of the foundry data provided. The key to having good designs (layouts) is that the DRC deck must be of high quality and accurate and must catch all the things you are not supposed to do in the layout. Most of the challenges in advanced node is in the FEOL where semiconductor physics and lithography play outsize roles. Issues that were not an issue at more mature nodes can manifest themselves as big problems at 7nm or 5nm. Process variation across the wafer and variation across a large die also present problems that were of no consequence in more mature nodes.
The real questions to be asked are as follows:
What is the role of test chips in SoC designs?
In complex SoC designs, there are many high-performance protocols such as LPDDR4/4x PHY, PCIe4 PHY, USB3.0 PHY, 56G/112G SerDes, etc. Each one of these IP are very complex in and by itself. If there is any chance of failure that is not detected prior to SoC (tapeout) integration, the cost of retrofit is huge. This is why the common practice is to validate each one of these complex IP in silicon before committing to use such IP in chip integration. The test chips are used to validate that the IP are properly designed and meet the functional specifications of the protocols. They are also used to validate if sufficient margins are designed into the IP to mitigate variances due to process tolerances. All high-performance hard IP go through this test chip/silicon validation process. Oftentimes, marginality is detected at this stage. In advanced nodes, it is also important to have the test chips built under different process corners. This is intended to simulate process variations in production wafers so as to maximize yields. Advanced protocols such as 112G, GDDR6, HBM2, and PCIe4 are incredibly complex and sensitive to process variations. It is almost impossible to design these circuits and try to guarantee their performance without going through the test chip route.
Besides validating performance of the IP protocols, test silicon is also used to validate robustness of ESD structures, sensitivity to latch up, and performance degradation over wide temperature ranges. All these items are more critical in advanced nodes than more mature modes. Test chips are vehicles to guarantee design integrity in bite-size chunks. It is better to deal with any potential issues in smaller blocks than to try to fix them in the final integrated SoC.
Test chips will continue to play a vital role in helping IP and SoC teams lower the risk of their designs, and assuring optimal quality and performance in the foreseeable future. They are not going away!
To read more, please visit https://semiengineering.com/test-chips-play-larger-role-at-advanced-nodes/