Cadence Showcases PCIe 7.0-Ready IP at PCI-SIG Developers Conference 2023

14 Jun 2023 • 2 minute read

PCIe 7.0 continues to progress through draft stage, IP enablement begins

The PCI-SIG announced that the PCI Express (PCIe) 7.0 specification has hit version 0.3 at the annual Developers Conference in Santa Clara on June 13, 2023. This represents a further doubling of the data rate to 128GT/s. The standard is expected to be finalized in 2025.

The PCIe standard has doubled the data rate approximately every three years

The 7.0 version will continue to use PAM4 signaling like 6.0 and maintain compatibility with prior versions with NRZ signaling for data rates 32GT/s and below. Cadence showcased its 128GT/s SerDes IP's receiver and transmitter capability at the event, demonstrating excellent electrical performance and margin. The demo was made possible with instrumentation from our partners Anritsu and Tektronix. Tektronix also hosted the same demo in their booth at the event, capturing the attention of a large number of attendees.

Cadence team demonstrating 128 GT/s SerDes IP to attendees

Cadence's first-in-the-industry IP subsystem for PCIe 6.0 was also a major draw. We showed off the electrical performance in our booth as well as with our partner Samtec. PCIe 6.0 is the first version of the spec to use PAM4 for signaling and Flit (flow control unit)-based architecture. Keysight Technologies showed off their exerciser/analyzer for PCIe 6.0 with our subsystem daughtercards. The Cadence subsystem IP for PCIe 6.0 has interoperated with the Keysight exerciser in both root-port and endpoint mode. Ali Ulas Ilhan from Cadence presented at the conference on interoperability-related topics for PCIe 6.0, highlighting the strides made by Cadence's design team in achieving these milestones. The electrical performance of the IP's receiver was also showcased with Samtec.

Cadence IP for PCIe 6.0 showcased at DevCon '23 (Cadence booth, Keysight Technologies, and Samtec demos. Ali Ilhan presenting at the conference)

Industry adoption of PCIe 5.0 continues apace. The Cadence IP for PCIe 5.0 is optimized for both power and performance and has achieved compliance in multiple workshops. The team showed off the subsystem IP for PCIe 5.0 operating on a commercially available motherboard, running stress tests that our customers typically use to qualify their products. Viavi Systems showed off their protocol analyzer for PCIe 5.0 with Cadence subsystem cards running eight lanes of PCIe traffic seamlessly at 32GT/s. The Cadence subsystem performance was so clean that the analyzer couldn't show error scenarios. They had to use an alternate card to demonstrate error cases!

Cadence IP subsystem for PCIe 5.0 demonstrated at DevCon '23 (Viavi Systems and Cadence demos)

Cadence continues to lead in PCIe development, offering solutions in advanced nodes for the latest versions of the standard. With a full suite of solutions encompassing PHYs, controllers, software, and Verification IP, Cadence is proud to be a member of PCI-SIG.