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DesignCon 2021, Drive World Conference, and Embedded Systems Conference are a joint event this year. Cadence had an opportunity to present at a session on behalf of PCI-SIG. The topic of the presentation is "PCI Express Technology: Accelerating Automotive Connectivity, from Infotainment to ADAS." I covered the portion on automotive trends and highlighted the various new automotive applications that are driving the transition to more advanced FinFET semiconductor process nodes as well as the adoption of higher speed protocols, especially usage of PCI Express. My colleague Arif Khan covered the use cases of PCI Express in automotive highlighting the attributes of PCI Express in compute performance, system performance, and silicon performance that make it an ideal protocol for next-generation automotive SoC across the spectrum of in-vehicle infotainment, in-vehicle networking, ADAS, and autonomous driving applications.
As we are all aware, the automotive industry is going through a lot of changes directly influenced by the trends in connectivity, autonomy, car sharing, and electrification. This leads to a lot of new applications and use cases in:
These applications are driving new chip solutions to require higher levels of integration and the use of more advanced FinFET processes from 16nm to 7nm and very soon 5nm. A lot of these new applications are more compute intensive as a result of the need for sensor fusion and AI (edge) acceleration as well as corresponding increases in data transmission and data storage.
Figure 1. Evolving in-vehicle network from domain to zonal architectures
Figure 1 illustrates the evolution of in-vehicle network from dedicated microcontroller-based systems to domain controller approach and the transition to a zonal network architecture that is underway. A corollary to this is that PCI Express technology is mission critical in domain and zonal networks. It has been adopted in multiple generations of infotainment and ADAS SoC and is a key protocol in chip-to-chip communications, central processing, and high-speed end-point connections.
Figure 2. PCIe standard has headroom for I/O bandwidth scalability
Figure 2 above shows the evolution of PCI Express standards from 2000 to 2024. I/O bandwidth doubles every three years. For example, from 8Gb/s for PCIe 3.0 released in 2010 to PCIe 4.0 at 16Gb/s in 2017, and advancing to PCIe 5.0 at 32Gb/s in 2019. We are now at the doorstep of PCIe 6.0 at 64G/s performance.
Figure 3: Automotive applications meet PCI Express
Figure 3 shows Infotainment, ADAS, V2X communication, connectivity applications, AI accelerators, to name a few, rely on intelligent systems that are driving the envelope for compute performance in bandwidth and application scalability. This places new requirements on systems for latency, virtualization, security, etc. These systems require SoCs to be implemented with power and thermal requirements and reliability specifications in advanced process nodes. Through years of protocol and implementation development, PCIe has been at the forefront of these performance vectors.
Figure 4: Compute drivers for use of PCIe protocols in automotive
Figure 4 shows an example use case around that is driven by compute needs in automotive SoCs. Autonomous vehicles and self-driving cars need 100s of Tera-ops (TOPs) of compute power. The degree of autonomy drives the amount of compute power needed. The number of sensors in a vehicle has grown dramatically. Depending on the system needs, automotive SoCs can be connected to multiple accelerators and GPUs. The PCIe standard and implementations have support for requirements that stem from this use case.
Backbones, storage, and connectivity are other example use cases we examine in our discussion at DriveWorld 2021. Our talk summarizes the key characteristics of standards and protocols that are essential for various use cases in the automotive segment and why PCIe is an ideal fit for this market and is being rapidly adopted. For a copy of the presentation or more information, Contact_IP@cadence.com.