Tensilica and Design IP Blogs

Cadence was the first IP provider to bring controllers for PCI Express (PCIe) 3.0 to the market and the lowest power 3.0 PHY at introduction. We're proud to continue the trend with our solution for PCIe 5.0 that continues to blaze the trail with new benchmarks for power, performance, and area.

Figure 1: I/O Bandwidth doubling every three years and PCI Specification Updates

The PCIe standard has been around for nearly 20 years. A diverse range of applications, bandwidth needs, and form factors drive the need for rate scaling of the protocol.  

Market drivers: Ethernet network adapters, solid state storage, persistent memories, and FPGA accelerators all reside on this ubiquitous interface. The PCI-SIG has tracked I/O bandwidth as it doubles every three years. The specification has scaled correspondingly.

Americans use 3 petabytes of data each minute. Google receives 3.8 million queries in about the same period of time (per data from 2018—twice as much they did in 2012!), Our insatiable demand for compute and data drive this need for I/O bandwidth. The SARS-CoV-2 genome was mapped in a matter of weeks in 2020 and vaccine trials accelerated through the use of technology—something that was unheard of just years ago. We are truly in the Zettabyte era. While video consumption was the primary driver in 2012, AI, machine learning, and a slew of intelligent applications have changed the computing landscape creating new possibilities as technology nodes, architecture, and protocols have evolved.

Power is the key: The challenge for the computing industry as it evolves along the forefront of this revolution is to meet these needs while being power-efficient. The information industry is often at odds with its image of environmental friendliness. Servers, storage, and networking equipment, and data centers often operate at an inefficient ratio of computing performance to energy consumption. Designing components with power efficiency from the ground up is key. The Cadence Subsystem for PCIe 5.0 is designed to be highly power efficient at the maximum data rate in both active and standby modes, with very low latency resumption times.

Figure 2: Cadence solution for PCIe 5.0 (PHY and Controller Subsystem SoC)

Subsystems and Compliance: When a new version of the standard enters the market, the PCI-SIG official compliance program has not yet launched. To build confidence, we need subsystems that demonstrate the full protocol solution working with a controller and PHY solution that can be tested with various equipment vendors for protocol and electrical tests. The Cadence subsystem SoC with an 8-lane solution accomplishes that and has been tested with multiple vendors and details will be shared in additional blogs and videos with our test partners. Follow this blog for further updates on this technology!

Visit our PCIe 5.0 technology page for the latest news on this technology from Cadence.