Since its inception, PCI Express® (PCIe®) has proliferated quickly to become ubiquitous in the modern digital world. Today, PCIe is an indispensable technology found in high-performance computing, AI/ML accelerators, network adapters, and solid-state storage, to name a few. In addition, recent advances in speed and latency of PCIe have allowed it to gain wider adoption within the memory hierarchy as well (e.g., persistent memory and DRAM via PCIe/CXL slot).

The evolution of new artificial intelligence/machine learning (AI/ML) applications and the accelerating shift of enterprise workload to the cloud continue to fuel explosive data traffic growth at an unprecedented pace. To address the projected data bandwidth requirement for the coming years, PCI-SIG unveiled the PCIe 6.0 specification in 2019, which doubles the transfer rate to 64GT/s! The final PCIe 6.0 specification is expected to be completed and approved by late 2021.

 

Figure 1: Projected growth of IO bandwidth and evolution of PCIe specification

 

 

PCI-SIG Developers Conference, May 2021

As the industry participates in PCI-SIG Developers Conference this week (May 25-26, 2021), there will be renewed focus on PCIe 6.0. Cadence is introducing its offerings in this space and we are taking this opportunity to dig a little deeper into the nuances of the standard and the implementation.

Key Challenges in PCIe 6.0

Doubling the I/O bandwidth beyond 32GT/s (PCIe 5.0 speed) to 64GT/s poses significant signal integrity (SI) challenges. The backward-compatibility requirement in PCIe mandates support for legacy channels (PCB + connectors + add-in card, etc.). At the 32GT/s NRZ signaling rate, the total channel insertion loss for these legacy channels can reach >36dB at the Nyquist frequency (16GHz). At 64GT/s NRZ signaling rate, the Nyquist frequency doubles to 32GHz and the channel’s frequency dependent loss increases to >70dB! The magnitude of signal loss through the channel makes the signal nearly indistinguishable from noise! Under such loss, transmitted data cannot be reliably recovered.

Bringing PAM4 to PCIe

PCIe 6.0 overcomes the channel loss challenge by changing signal modulation scheme from Non-Return-to-Zero (NRZ) to Pulse-Amplitude-Modulation 4-Levels (PAM4). PAM4 is a multi-level signaling technology that transmits 2 bits per unit interval (UI) as opposed to NRZ, which transmit only 1 bit per UI (see Figure 2). PAM4 signaling for PCIe 6.0 is advantageous because by transmitting 2 data bits per UI, data rate is effectively doubled without doubling the Nyquist frequency. Channel loss, therefore, is kept at the same manageable level as PCIe 5.0.

 

Figure 2:  PAM4 Modulation

However, upgrading PCIe to use PAM4 signaling brings with it a new set of difficult challenges and complexities that need to be overcome—see our newly published white paper: “Pushing the Envelope with PCIe 6.0: Bringing PAM4 to PCIe”. Fortunately, PAM4 is not new to Cadence. As early as 2015, Cadence invested in developing 112Gb/s PAM4 technologies through the acquisition of Nusemi. Today, Cadence is recognized as a leading provider of 112G/56G PAM4 SerDes IP in multiple advanced FinFET nodes with customers having achieved successful silicon designs with our IP.

Protocol Updates for Efficiency

The PIPE interface to the controller was updated to version 6.0 with further improvements for latency reduction. 

The PCIe 6.0 spec introduces the concept of Flow Control Unit (FLIT) to work efficiently with the required Forward-Error-Correction (FEC) for PAM4, offering lower latency in the most frequently used configurations for the most common payload sizes.

Earlier generations of PCIe supported power savings through dynamic link width change along with the low-power states. However, the dynamic link width change interrupted the traffic flow during the process. PCIe 6.0 introduces a new low power state ‘L0p’ that allows power scaling proportional to the bandwidth without interrupting traffic. 

Complete IP Solutions for PCIe 6.0 from Cadence

Figure 3: PCIe PHY and Controller Solution from Cadence

Cadence is leading the way to bring PCIe 6.0 IP solutions to address the forthcoming needs of the rapidly evolving technology landscape at the cutting edge. Leveraging state-of-the-art PAM4 technologies from Cadence’s extensive portfolio of production-proven 112G/56G PAM4 Ethernet PHY IP and its long-standing history in PCIe (Cadence has been a leading supplier of PCIe PHYs and controllers for nearly two decades), Cadence is well-positioned to bring the best-in-class PCIe 6.0 PHY and Controller IP to the market. 

Please visit Discover PCIe for more information.