First Look: Cadence Subsystem SoC for PCIe 5.0

If a picture is worth a thousand words, a video tells you the entire story. Cadence's subsystem SoC silicon for PCI Express (PCIe) 5.0 demo video shows you how we put together the latest technology in TSMC's advanced FinFET technology to bring to market a compelling, low-power solution and tested it with the latest industry test solutions available.

The subsystem contains Cadence's PHY and dual-mode (root port and end-point) controller solution for PCIe 5.0 in an 8-lane implementation. In past incarnations of the PCIe specification, it was possible to test the PHY silicon with a controller in an FPGA. As the bandwidth needs of the protocol have scaled, the PIPE interface between PHY and controller is faster and the controller needs to run at higher speeds as well, making multi-lane FPGA implementations that run at full speed impractical. 

Implementing an SoC solution that proves a full protocol stack demonstrates capabilities that we can uniquely deliver as an IP provider that has built complete solutions for many generations of the specification.

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Figure 1: High-level PCIe 5.0 SoC block diagram

This complete subsystem in silicon allows us to test against available server platforms with ease which is critical for a new standard. Cadence is making this platform available to its customers and partners.

Silicon testing with industry partners:  Test vendors are evaluating their offerings and we have used this platform to successfully test key parameters for compliance with the leading platforms available today. We are looking forward to wider interoperability testing with additional server platforms as they become available. The official compliance program for PCIe 5.0 will launch in the coming year or later and we look forward to those events!

Figure 2: PCIe 5.0 TX EYE

Visit our PCIe 5.0 technology page for the latest news on this technology from Cadence.