The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center use cases, high-throughput die-to-die connectivity is more essential than ever. Cadence has already demonstrated its 32G UCIe standard package IP subsystem on TSMC’s 3nm (N3P) process technology. To bring even greater flexibility to our mutual customers, Cadence announces that it has taped out its IP subsystem for the 32G UCIe advanced package on TSMC’s 3nm (N3P) process technology. Building on seven years of expertise in die-to-die solutions and the success of multiple UCIe IP subsystem test chips, this next-generation product delivers improved performance and flexibility while maintaining the reliability and precision proven by its predecessors.

The 32G UCIe-AP solution builds on its predecessor, the 32G UCIe-SP, as well as the 16G UCIe-SP and UCIe-AP solutions. Key features include:

• High-Speed Data Transfer Ranging from 4Gbps to 32Gbps: This IP supports all UCIe data transfer rates from 4Gbps to 32Gbps, offering flexibility across various customer applications. This broad speed support makes the IP ideal for diverse use cases, providing scalable performance to meet the requirements of both low-power systems and high-throughput systems.
• Optimized Design for 32Gbps Speed and Wide Interoperability: The IP is optimized to operate seamlessly at the UCIe specification speed of 32Gbps, ensuring robust interoperability with any UCIe solution. This optimization enables the best performance metrics and broader interoperability.
• Universal Interoperability for Various Transmitter and Receiver Configurations: The UCIe transmitter in Cadence’s IP supports both half-rate and quad-rate UCIe receiver implementations, ensuring broad compatibility across various configurations. With the ability to generate clocks up to 16GHz, this IP provides robust support for data rates up to 32Gbps, ensuring full interoperability in diverse UCIe applications.
• Self-Calibrating Capabilities and Hardware-Based Bring-Up with No Firmware Requirements: A key feature of Cadence’s UCIe solutions is their self-calibration functionality and hardware-based bring-up, which eliminates the need for firmware intervention during system initialization. This significantly simplifies the setup process by removing the need for firmware loading.
• At-Rate Loopback for Wafer Sort and Validation: The IP features at-rate loopback at 32Gbps, enabling efficient wafer sort—a key feature for D2D solutions—and simplifying packaged part validation. Additionally, the full die-to-die (D2D) loopback mode ensures comprehensive validation across the entire link, including the channel, from one die to its partner and back, offering complete testing coverage for high-reliability systems.
• Integrated Internal PLL: Like all previous Cadence UCIe IP, this IP includes an internal Phase-Locked Loop (PLL) that autonomously generates the necessary Lclk and high-speed clocks within the IP. The user only needs to supply a 100MHz reference clock, with the option to provide the Lclk from the SoC. This allows for simplified clock management, streamlined integration, and reduced system complexity.
• Robust Performance Under Extreme Operating Conditions: Cadence’s UCIe IP solutions feature a “Maintenance Mode” that performs regular background runtime recalibration to ensure uninterrupted operation, even under changing conditions such as supply voltage and temperature drifts (ranging from -40°C to 125°C), covering the full industrial range.
• Support for Vendor-Defined Messaging Over Sideband Links: The IP supports vendor-defined messages over sideband links, fully compliant with UCIe specifications. This feature ensures effective communication and control across the die-to-die interconnect, enhancing system integration. It is included in both the 16Gbps and 32Gbps versions of our UCIe IP solutions.
• Broad Protocol Support: Cadence’s 32G UCIe IP also offers broad protocol support to enable pre-validated, high-performance, low-latency, and low-power subsystems for any application.

Cadence's new 32G UCIe-AP IP subsystem marks a major advancement in die-to-die connectivity. It offers high performance, power efficiency, and integration, supporting a range of advanced packaging options. This IP builds on the reliability and precision of Cadence’s previously proven Gen2 UCIe-SP and Gen1 UCIe-SP and UCIe-AP solutions, continuing to support features such as self-calibrating capabilities, hardware-based bring-up, and robust performance under varying conditions. As a contributing member of the UCIe consortium, Cadence is helping to shape the future of the chiplet ecosystem and meet the needs of modern high-performance computing, data centers, and AI/ML applications.

For further information or inquiries, please contact us to explore how our UCIe IP can support your projects. Learn more at www.cadence.com.