UCIe Interoperability Between Intel and Cadence

Intel and Cadence are collaborating on an initiative to demonstrate interoperability between Intel’s UCIe IP and Cadence’s UCIe IP.

UCIe is the latest emerging open specification defining the interconnect between two die links in a system in package (SiP). UCIe is expected to enable power-efficient and low-latency chiplet solutions as heterogeneous disaggregation of SoCs becomes mainstream to overcome the challenges of Moore’s Law. The UCIe 1.0 standard, dated February 24, 2022, first became available in March 2022. A newly updated UCIe 1.1 specification was recently released and announced on August 8, 2023.

Emerging new standards often present unique challenges and limited opportunities for interoperability. Intel and Cadence have collaborated on simulation interop initiatives for a number of years and previously demonstrated CXL and PCIe-IDE interoperability as these new standards emerged. Intel and Cadence are now working together to demonstrate UCIe interoperability of Intel’s UCIe IP and Cadence’s latest UCIe IP solutions. The first step towards this collaboration is a demonstration of pre-silicon RTL co-simulation interoperability.

The lack of a platform for interoperability testing provides a challenge on how to show that an IP was developed according to the UCIe specification. This is especially critical as the standard is evolving from Revision 1.0 in 2022 to Revision 1.1 in 2023. The UCIe simulation discovery process developed by Intel and Cadence was designed to ensure both Intel and Cadence PHYs are functionally interoperable per the UCIe specification and to make the debugging of issues that may arise during the interoperability test easier and more efficient.

The Figure 1 diagram illustrates the UCIe simulation framework of the RTL interoperability environment between Intel and Cadence.

Figure 1. UCIe simulation framework

The Cadence UCIe advanced package PHY model with x64 lanes was used for pre-silicon verification with Intel’s UCIe-generated vectors. The Cadence UCIe layers consisted of testbench-style bus functional models (BFMs) that responded to incoming requests from Intel UCIe vectors and initiated outbound requests via Verilog tasks. The UCIe sideband was used for initialization, link training, and messaging between the die links. Parameter information, which could include data rate negotiation or link training results with the link partner, was exchanged over the sideband interface.

The link training state machine (LTSM), shown in Figure 2, is defined in the UCIe specification. The link states from RESET to ACTIVE were followed at a high level to step through each state for initialization.

Figure 2. LTSM – From the UCIe Specification, Revision 1.1

During interoperability testing, in addition to verifying the proper operation of the LTSM, we were able to monitor and verify important interoperability steps such as PHY lane check order, ensuring each state is entered and exited successfully. Regression testing and interoperability simulation between the established die links was an opportunity to improve the robustness of both PHYs. It also aimed to validate the designs against various areas of the UCIe specification in order to improve the quality of both products.

The next step is to enable controller simulation interoperability by building on top of the physical layer, similar to the controller interoperability work performed by Intel and Cadence since 2020 for CXL1.1, CXL2.0, and PCIe-IDE. The application layer enhancement with the addition of the controller, FDI interface, and client interfaces will be tested using the RAM model.

In conclusion, as the UCIe specification continues to evolve, there is a drive to set up an open standard ecosystem to enable design IP, verification IP, and testing practices for compliance. To keep up with the rapid pace of the chiplet ecosystem expansion, simulation, and interoperability testing between different sources of UCIe IP is essential. As in the case of Intel and Cadence described above, it helped to quickly and more confidently validate the UCIe design IP, delivering a better product.

To learn more, visit the Cadence UCIe PHY and Controller Design IP page or Contact Us.

More details on UCIe VIP are available on the Cadence Verification IP Portfolio page.

Learn more about the Intel and Cadence Pre-Silicon Simulation Interoperability CXL Case Study.

For more information on UCIe in general, visit the UCI Express website.