Cadence San Jose Hosts JEDEC LPDDR (Low-Power DDR) Task Group Meeting

Low-power DDR (LPDDR) SDRAM has been one of the most widely used memories in the semiconductor market today. It is used in a diverse set of applications that span mobile/handheld devices, IoT, client and server, automotive, virtual reality/gaming consoles, robotics, data centers, and artificial intelligence (AI) applications, just to name a few.

On April 10 and 11, 2024, Cadence hosted the JEDEC LPDDR Task Group, which is designated to define the memory standard for the next generation of low-power DDR memories. This is the third year in a row that Cadence has hosted the JEDEC LPDDR Task Group meeting, with Cadence being the venue for similar face-to-face meetings in 2023 and 2022.

Here is some background on JEDEC. For over 50 years, JEDEC has been the global leader in developing open standards for the microelectronics industry, and the JEDEC membership includes industry-leading semiconductor companies.

The meeting was well attended with more than 25 member companies joining the meeting in person and remote with in person meeting participants includes people from some of the most important semiconductor companies in the world.

This face-to-face meeting enabled leaders who are part of JEDEC LPDDR TG to make significant progress on the next-generation LPDDR standard.

“The JEDEC LPDDR Task Group face-to-face meeting is a significant step in defining the future Low-Power DRAM industry standards for next-generation applications,” said Osamu Nagashima of Micron and Chair of the JEDEC LPDDR Committee. “Cadence, being a valued task group member, has graciously hosted this meeting for three consecutive years.” 

Cadence Memory IP system solutions offer world-class LPDDR, DDR, GDDR, and HBM PHY and Controller IP that are flexible and configurable to support a wide range of applications.

Cadence VIP (Verification IP) offers a compressive memory subsystem solution that includes memory models for all generations of LPDDR, DDR DRAMs, Dual Inline Memory Modules (DIMM) DFI Memory Controller/PHY VIP, and a System VIP (Verification IP).

If you have any queries, feel free to contact us.

More information on Cadence LPDDR5/LPDDR5X VIP is available at Cadence VIP Memory Models Website.

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