Cadence Targets Automotive Market Demands with UCIe

Cadence has become a contributor-level member of the Automotive Working Group in the Universal Chiplet Interconnect Express (UCIe) Consortium. Last year, the Consortium ratified the UCIe specification, which was established to standardize a die-to-die interconnect for chiplet components from multiple vendors. Cadence currently actively engages in the electrical, form factor and compliance, manageability and security, protocol, systems and software, and marketing working groups to help steer and develop the new chiplet standard.

“We are delighted to be part of the UCIe chiplet ecosystem, focusing on developing low-latency, high-quality UCIe controller and PHY solutions for a number of key markets, including automotive. Cadence has a wealth of experience in delivering automotive controller and PHY IP solutions across its portfolio. These solutions support a number of automotive-focused features such as CRC error detection, error code correction (ECC), datapath and control path parity, one-hot finite state machines, and interface timeouts.” —Gary Dick, Engineering Group Director at Cadence.

The UCIe Consortium formally held Automotive Task Force meetings in April 2023 to address the needs of chiplets in automotive applications. There was a peak attendance of almost 100 people, and the goal to set up an Automotive Working Group in UCIe received presentations from multiple companies. There were requests to add features to the UCIe standard for automotive constraints and requests for new protocols to be supported.

Challenges and opportunities for UCIe to serve the automotive segment were discussed with a broad group of contributors. Companies with expertise and experience in the automotive markets presented material to impact UCIe’s future course of action to create an infrastructure around automotive safety, detecting and preventing potential failures, repairing detected failures, and the importance of a low FIT rate.

The UCIe Protocol Working Group has addressed mainband data integrity protection. As a part of ECN1 in the next UCIe Rev 1.1 version of the specification, the main data path can have CRC and retry implemented for a streaming controller. Automotive use cases can lean heavily on CRC as the primary safety mechanism for the main data path.

The sideband runs at 800MHz and includes parity for error detection. The BER for data rates 8Gbps and below is expected to be 1e-27, according to the UCIe standard, and translates to an extremely low FIT rate. However, parity errors on the sideband can translate to fatal uncorrectable errors on the link and can be considered insufficient integrity protection for ASIL compliance. Cadence is providing a proprietary proposal to ensure sideband message protection and integrity for automotive safety.

“Cadence is excited to contribute superior and easy-to-integrate UCIe automotive IP solutions to the standardized chiplet ecosystem. Enabling automotive safety and robust automotive IP for UCIe provides re-usable solutions for scalability in chiplet adoption.” —Rishi Chugh, VP of Marketing at Cadence.

Cadence is well-positioned to implement automotive UCIe for chiplet solutions. Cadence is an industry leader with a track history of automotive products available on PCIe/CXL, LPDDR/GDDR, USB, MIPI C/D-PHY and I3C, 10GBase-KR, USXGMII/QSGMII/SGMII, xSPI, SD/eMMC, and ONFi/Toggle.

Cadence’s adoption of automotive UCIe to expand its automotive portfolio enables customers to partition their automotive application designs in a constant growth trend.

Learn more about Cadence IP for the UCIe standard.