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Accelerating Chiplet Innovation with a New Partner Ecosystem

The semiconductor industry is currently undergoing a massive shift. As we push the…

Mick Posner
• 4 min read
IP , featured , chiplets , physical ai , OCP FCSA

The Memory Imperative for Next-Generation AI Accelerator SoCs

The tremendous growth in large language model (LLM) size corresponds with an equally…

Subash Peddu
• 4 min read
featured , HBM , SoC , AI

Scale-Up and Scale-Out IP for Optical Interconnect for Accelerated Computing

Optical connectivity is foundational to modern data centers, enabling high-bandwidth…

HW202512191014
• 4 min read
featured , AI data center , AI factory , Data Center architecture
SoC and IP
Latest blogs

Cadence Achieves Successful Silicon Validation of 1st IP Test Chips on Intel 18A

Cadence has reached an important milestone in its collaboration with Intel Foundry…

• 3 min read
ucie , Design IP , 112g , SerDes , PCIe 6.0 , Intel Foundry

Beyond PCIe Compliance: Why Stress Testing Is Crucial for Edge AI Deployments

Passing PCI Express (PCIe) compliance is different from being ready for the field…

• 4 min read
Edge AI , Design IP , validation , PHY , Edge Computing , compliance , stress testing , PCIe , SerDes IP

Cadence Demonstrates PCIe 8.0 PHY at PCI-SIG DevCon 2026

The accelerated growth in data processing and storage demands across HPC data centers…

• 2 min read
AI data center , data center , hyperscale data center , AI factory

Securing Scale-Up AI: Cadence’s Complete UALink Solution

As AI systems continue to scale, adding more compute is no longer the biggest challenge…

• 4 min read
security , IP , UALink , UALinkSec , datacenter , AI

PCIe 7.0 for AI Factories: Why Bandwidth Alone Isn’t Enough

AI factories are scaling rapidly. Training large models and delivering low‑latency…

• 1 min read
Design IP , AI data center , AI Inferencing , DIP , AI Factories , PCIe 7.0 , PCIe , AI training , PCIe 6.0

SOCAMM: Modernizing Data Center Memory with LPDDR6/5X

Small Outline Compression-Attached Memory Module (SOCAMM) has made its way into the…

• 3 min read
Design IP , AI Inferencing , AI Factories , ip cores , lpddr5x , AI training , Lpddr6

One PHY, Zero Tradeoffs: Multi-Protocol PHY for Edge AI Interface Consolidation

From smart cameras to autonomous vehicles and compact edge servers, edge AI is pushing…

• 2 min read
Automotive , Edge AI , Design IP , PHY , DisplayPort , Ethernet standards , USB , Ethernet , PCIe , PCIe Gen3 , SerDes , SerDes IP , PCIe PHY , multi-protocol

Understanding the Difference Between a Monolithic SoC and a Chiplet

I am often asked, "What is the difference between a traditional SoC die and a chiplet…

• 7 min read
Design IP , chiplets , OCP FCSA , ip cores , lpddr5x , Arm CSA , CHI-C2C

Transforming the Automotive Experience with Cadence Tensilica DSPs

Experience Innovation at Embedded World 2026 The automotive industry has shifted…

• 1 min read
Automotive , DSP , IP , Tensilica DSPs , SoC , ip cores , Tensilica , semiconductor IP

Accelerating Chiplet Innovation with a New Partner Ecosystem

The semiconductor industry is currently undergoing a massive shift. As we push the…

• 4 min read
IP , featured , chiplets , physical ai , OCP FCSA , OCP , Arm CSA , ARM

The Memory Imperative for Next-Generation AI Accelerator SoCs

The tremendous growth in large language model (LLM) size corresponds with an equally…

• 4 min read
featured , HBM , SoC , AI

Accelerating Chiplet Interoperability

In the chiplet marketplace, the vision of a library of chiplets that can be mixed…

• 2 min read
chiplets , OCP FCSA , CSA , OCP , FCSA , Arm CSA , ARM

Cadence Tapes Out 32GT/s UCIe IP Subsystem on Samsung 4nm Technology

With the rapidly increasing connectivity demands driven by AI/ML and HPC/datacenter…

• 3 min read
ucie , Design IP , chiplets , d2d

CES 2026 Recap: Trust Built on a Real, Working eUSB2V2 System Demo

Nothing builds trust like a real working system. That was the guiding principle…

• 4 min read
controller IP , Design IP , cadence , CES , PHY , USB , USB 2.0 , semiconductor IP , Design IP and Verification IP , AI

Scale-Up and Scale-Out IP for Optical Interconnect for Accelerated Computing

Optical connectivity is foundational to modern data centers, enabling high-bandwidth…

• 4 min read
featured , AI data center , AI factory , Data Center architecture

Heterogeneous Multicore Using Cadence IP

Build a Heterogeneous multicore with RISC-V, Xtensa DSPs and Janus NoC. Off-load…

• 6 min read
NoC , cadence , Tensilica , Xtensa , heterogeneous , SystemC , multicore , FPGA , multiprocessing

From Spec to Silicon: Successful Physical AI System Chiplet Bring-Up

The semiconductor industry is advancing at an unprecedented pace, driven by the need…

• 7 min read
ucie , IP , chiplets , physical ai , lpddr5x , ARM , AI

The Power of Shifting Left: Cadence Accelerating Innovation with Arm

In semiconductor design, projects are remembered for their extremes—legendary successes…

• 3 min read
ucie , xcellium , IP , featured , PHY , Palladium , PCIe , neoverse , DDR , ARM

Rethinking Edge AI Interconnects: Why Multi-Protocol Is the New Standard

Modern compute systems have evolved beyond reliance on a single dominant interface…

• 2 min read
Design IP , PHY , AI Inferencing , 25G Ethernet , Edge Computing , 10G-KR , PCIe 5.0 , Ethernet , PCIe , SerDes , SerDes IP , Concurrent Multi-protocol Support , Multi-link , multi-protocol , AI

Running Optimized PyTorch Models on Cadence DSPs with ExecuTorch

By Vijay Pawar of Cadence and Matthias Cremon of Meta Introduction Deploying…

• 2 min read
IP , Tensilica , HiFi DSP

Powering Scale Up and Scale Out with 224G SerDes for UALink and Ultra Ethernet

As AI workloads grow in scale and complexity, networks are challenged to keep up…

• 3 min read
Design IP , featured , 224G-LR , 224G SerDes , UALink , ECOC , Ultra Ethernet

Accelerate Automotive System Design with Cadence AI-Driven DSPs

The automotive industry is on the brink of a transformative era powered by intelligence…

• 6 min read
Automotive , infotainment , autonomy , In-cabin sensing , lidar , Xtensa CPU , radar , Tensilica , vision , ADAS

A Hybrid Subsystem Architecture to Elevate Edge AI

The world of artificial intelligence is moving beyond the cloud and into our everyday…

• 4 min read
controller IP , DSP , cadence , NeuroEdge 130 , IoT , Tensilica DSPs , SoC , ip cores , Tensilica , semiconductor IP , AICP

From 12 Hours to 2: How AI Accelerates Automotive Quality Assurance

In the fast-paced world of Industry 4.0, quality assurance (QA) is no longer just…

• 2 min read
Automotive , Regression , Verisium Manager

Ensuring End-to-End Traceability for Safety-Critical Applications

There is now a direct interface between the Midas Safety Platform and popular requirements…

• 4 min read
Requirement Management System , Safety Solution , DOORS , functional safety , RMS , Safety , Product Lifecycle Management , Safety Analysis , JIRA , Traceability , Jama , Polarion , PLM , Codebeamer , Safety Compliance

Boosting AI Performance with CXL

AI workloads are outpacing traditional memory architectures—but CXL®︎ offers a smarter…

• 3 min read
CXL , Design IP , IP , controller , PCIe

The Next-Generation UCIe IP Subsystem for Advanced Package Designs

With the rapidly increasing connectivity demands driven by AI/ML and HPC/data center…

• 3 min read
ucie , Design IP , featured , TSMC , die-to-die , HPC , AI

Cadence Powers AI Infra Summit '25: Memory, Interconnect, and Interface Focus

AI is driving a new semiconductor renaissance—it's no longer just a workload, but…

• 2 min read
controller IP , ucie , Design IP , IP , Memory , AISummit , 224G-LR , HBM , hbm4 , memory IP , Ethernet , AI training , Ethernet PHYs , UALink , AI , data centers , AIInfraSummit
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