From Spec to Silicon: Successful Physical AI System Chiplet Bring-Up

The semiconductor industry is advancing at an unprecedented pace, driven by the need for higher performance, greater integration, and maximum efficiency. With Moore's Law slowing, innovative approaches like chiplet-based architectures have taken center stage, especially for physical AI designs. We are excited to announce a major milestone: the successful silicon bring-up of the Cadence System Chiplet, a core component of our physical AI chiplet platform.

In this post, we will review the strengths of the physical AI chiplet platform as we detail the multi-phase silicon bring-up journey of our System Chiplet, including technical highlights such as the Cadence UCIe high-speed die-to-die interconnect and LPDDR5X 9600 memory interface validation.

The Power of the Physical AI Chiplet Platform

Traditional SoCs were typically monolithic, with all functions housed on a single silicon die. As demand for specialization and higher performance surged, however, this model revealed significant limitations in manufacturing complexity, yield, and cost.

For applications such as automotive ADAS, robotics, drones, and aerospace and defense, the physical AI chiplet platform answers these challenges with a modular design. By disaggregating a large SoC into separate, specialized chiplets for (1) compute, (2) system management with memory and I/O, (3) AI engines, and (4) optional domain-specific functions, the platform enables cost reduction, customization, and flexible configurations. At the center of this architecture is the Cadence System Chiplet, which orchestrates communication, manages resources, and serves as the backbone of the entire platform.

Figure 1. Cadence's Physical AI Chiplet Platform

The Silicon Bring-Up Journey: Step by Step

Engineering a chiplet-based platform from concept to working silicon is a meticulous, multi-stage process. The successful bring-up of the System Chiplet, a critical component of the physical AI chiplet platform, showcases Cadence's deep technical expertise and demonstrates the maturity of this modular approach. The platform integrates multiple instances of the same System Chiplet die, enabling the system to mimic multiple application use cases.

Figure 2. Package image diagram and actual photo of package of dies

Milestone 1: System Platform Initialization

Achieving initial power-on and successful platform initialization marked the first major milestone. The hardware team coordinated power delivery, clocking, and basic connectivity across all chiplets, verifying that system-level reset and bring-up sequences performed as intended. Debug capabilities are embedded in the always-on power domain, which ensures die access before the UCIe die-to-die interconnect links are initialized. This foundational step enabled further functional validation of interfaces and prepared the platform for subsequent milestones. The single die configuration booted to the command prompt within a day of hardware and software setup. This was achievable as both the hardware and software had been pre-silicon verified in simulation and emulation.

Milestone 2: UCIe Die-to-Die Interface Bring-Up

After the individual die initialization, it was time to move on to the multi-die chiplet-to-chiplet configurations. This pivotal step in the process involved bringing up and validating the UCIe high-speed die-to-die interface, which is essential for reliable chiplet communication. One chiplet was configured as the multi-die initiator, and after completing its own secure boot, it went on to manage the initialization of the secondary chiplet. This is a baseline function of the Cadence Chiplet Framework, which I will share more about later. The engineering team carefully executed power sequencing, link training, and initial handshake routines across chiplets. Through exhaustive testing and measurements, we verified signal integrity, error rates, and lane reliability. Importantly, and with a significant margin, we successfully validated the 32Gb/s UCIe performance across the 25mm link (the maximum link length per UCIe specification) and shorter 7mm links implemented in the package. This successful milestone not only proved interoperability between chiplets at the raw electrical and protocol layers but also validated the robustness of the Cadence UCIe implementation.

Figure 3. UCIe-SP32G RX Eye Opening (25mm Link)

Milestone 3: LPDDR5X 9600 Memory Interface Bring-Up

Maximizing AI performance requires high-speed memory access, deeply integrated into the system's core architecture. The bring-up and validation of the LPDDR5X 9600 memory interface represented the next major Cadence System Chiplet bring-up accomplishment. It includes the latest Cadence LPDDR5X IP solution, with the interface brought online and successfully trained for robust operation at 9600 Mb/s. With the memory subsystem operational, extensive stress tests—including demanding read/write patterns and high-bandwidth streaming—confirmed error-free, sustained high performance even with concurrent access across chiplets. Each chiplet in the two-chiplet system enables a unique configuration, so multiple realistic use cases could be validated. Test cases included disabling the memory subsystem in one chiplet and having the other chiplet read and write to memory across the chiplets' UCIe connections. Another test case configured the LPDDR5X interfaces on each chiplet, building a shared memory structure. The Cadence System Chiplet's central management ensured optimal memory utilization, empowering the physical AI chiplet platform to deliver advanced AI throughput and efficiency.

Figure 4. LPDDR5X Write Eye, excellent electrical margin (overclocked at 14.6Gbps)

Milestone 4: Chiplet Framework Validation

Another fundamental milestone centered on testing the Cadence Chiplet Framework itself, which served as a key criterion for the platform's success. This framework underpins the platform's modular architecture, defining standards for integration, discovery, management, secure boot, functional safety, and coordinated function among heterogeneous chiplets. The validation process included orchestrating complex operations across combinations of chiplets, verifying that each functional block could be independently managed, dynamically allocated, and automatically detected by the platform. Inter-chiplet workflows, error reporting, and platform-level configuration were demonstrated to operate seamlessly, confirming both the extensibility and robustness of the modular design. Proven Chiplet Framework integration ensures the platform supports rapid innovation, simple scalability, and reliable interoperability as new chiplets and workloads are introduced.

Figure 5. Cadence Chiplet Framework capabilities

Milestone 5: Functional and Performance Validation

The functional and performance validation phase involved rigorous testing of the platform under various real-world scenarios to ensure it meets expected standards. Comprehensive benchmarks were conducted to measure data throughput, latency, and power efficiency across diverse AI workloads. Cadence utilized several industry-standard benchmarks available through TinyML, including object detection. Because TinyML is a branch of machine learning focused on AI on the "edge," there is no need to rely on power-hungry cloud processing. Stress tests further validated the system's ability to handle peak performance conditions without degradation, stressing individual chiplets as well as multi-chiplet modes. The results confirmed that the platform achieves both high reliability and competitive performance metrics, positioning it as a robust solution for next-generation physical AI applications.

Finally, the focus moved to specific system-level validation of functional areas not covered by the previous application cases. Tests covered a range of scenarios, from standard data transfers to complex AI task execution, each coordinated by the Cadence System Chiplet and distributed over chiplets with identical or differing configurations to mimic additional application use cases. The platform excelled, with no errors in high-volume data exchange, consistent performance under AI workloads, and robust overall system integration. The System Chiplet proved its critical role as the nexus for communication and orchestration within the platform, while the use of multiple chiplets multiplied the AI throughput and provided flexible performance scaling utilizing a multi-die chiplet-based modular design.

What This Success Means for Future Physical AI Platforms

The successful bring-up of the Cadence System Chiplet, as part of a physical AI chiplet platform, marks a new standard for modular, high-performance semiconductor design.

1. De-Risking Advanced System Integration: Demonstrating a fully operational System Chiplet intertwined with memory and other critical interfaces gives future product teams confidence in adopting this platform for powerful physical AI systems, moving the product from concept to market-ready.
2. Accelerating Ecosystem Growth: By validating not only open standards but also the System Chiplet approach within a comprehensive platform, we move closer to an ecosystem where designers can reliably combine chiplet designs.
3. Enabling Powerful and Flexible Architectures: With the System Chiplet serving as the heart of the physical AI chiplet platform, next-generation automotive ADAS, drones, robotics, and aerospace and defense designs can now benefit from the flexibility and scalability once limited to complex and costly monolithic SoCs.

Physical AI platforms are poised to transform multiple industries, with use cases spanning automotive, robotics, drones, and aerospace and defense. This versatility highlights the platform's adaptability to the complex requirements of safety, autonomy, and high-performance computing found in these sectors.

Final Thoughts

Transitioning from design to functioning silicon on a modular platform, especially for physical AI applications, is a complex, rewarding journey. Our successful bring-up highlights the decisive role of the Cadence System Chiplet as an essential component of the physical AI chiplet platform and Cadence's role in jump-starting the realization of a chiplet marketplace. While standardized die-to-die interconnects like UCIe facilitate chiplet interoperability, the real impact lies in the Cadence platform's integrated design and silicon-proven chiplet framework managing a multi-die chiplet system.

We are proud to help shape a new era of scalable, adaptable, and high-performance physical AI systems, which are at the core of tomorrow's most powerful edge AI technology solutions. Cadence is ready to help our customers realize their chiplet ambitions.

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