PCIe 7.0 for AI Factories: Why Bandwidth Alone Isn’t Enough

AI factories are scaling rapidly. Training large models and delivering low‑latency inference now requires thousands of GPUs, accelerators, memory devices, and I/O endpoints. System efficiency increasingly depends on how data moves across the infrastructure, not compute power alone.

PCI Express^® (PCIe^®) has long been the interconnect standard for scale‑up systems, connecting CPUs, GPUs, NICs, and memory within the node. By doubling link speed to 128GT/s, PCIe 7.0 delivers up to 512 GB/s of bidirectional bandwidth per x16 link.

Traditional PCIe ordering models were designed for less complex systems, often forcing unrelated traffic to serialize. Even Relaxed Ordering and ID‑based Ordering retain fabric‑enforced constraints that introduce inefficiencies and limit concurrency.

PCIe 7.0 targets next‑generation, highly parallel workloads, including AI training and inference, which generate numerous concurrent and independent transactions. However, ordering itself must evolve to fully utilize PCIe 7.0's increased bandwidth and optimize these AI systems.

Unordered I/O (UIO) allows devices to determine when ordering is unnecessary. Rather than relying on the fabric to enforce sequencing, UIO shifts responsibility to the endpoints. This enables higher parallelism, lower latency, and better sustained utilization of PCIe links for AI workloads.

With the evolution of data centers into AI factories, interconnect design has become as critical as compute and memory—across both scale‑up architectures within the node and scale‑out fabrics connecting accelerators and memory across systems. In this environment, PCIe serves as the foundational backbone for control and data movement, orchestrating connectivity, ordering, and efficiency across the entire interconnect hierarchy.

Cadence's PHY and controller IP for PCIe 7.0 are designed to support these complex architectures underlying today's AI infrastructure, enabling high‑bandwidth, low‑latency data movement while accommodating advanced ordering models like UIO.

To learn why bandwidth alone is no longer sufficient and how PCIe ordering is evolving to maximize system efficiency, read the PCIe 7.0 fundamentals mini-series on EDN:

 PCIe 7.0 fundamentals: Baseline ordering rules

 PCIe 7.0: Addressing legacy ordering limitations with UIO

 Learn more about Cadence PCIe and CXL IP