Cadence Drives Next-Gen Memory and Connectivity at FMS 2025

As AI data centers continue to scale up and out to accommodate increasingly compute-intensive workloads, ensuring memory interfaces and high-speed interconnects are architected for fast and efficient data movement has never been more critical. Cadence continues to invest significant engineering effort to deliver advanced, user-friendly IP solutions across a range of essential protocols, two of which were on display at the recent Future of Memory and Storage (FMS) conference in Santa Clara, CA.

A PCIe 6.0 interoperability setup and a 3nm DDR5 MRDIMM Gen2 silicon demo attracted attention from across the industry and showcased Cadence's leadership in interconnect IP and high-performance memory. The standout live demonstrations in the Cadence booth highlighted Cadence's deep engineering expertise and commitment to advancing cutting-edge industry protocols.

First PCIe 6.0 IP Subsystem in Silicon: Configurable, Compliant, and Low-Power

Cadence's interoperability demo brought PCIe 6.0 to life with a fully integrated IP subsystem that enabled seamless communication between its PCIe 6x8 controller root port and endpoint. Real-time traffic monitoring via a LeCroy Analyzer highlighted the system's interoperability and performance, demonstrating Cadence's leadership in enabling high-speed connectivity for next-generation storage and compute systems.

DDR5 @ 12.8Gbps MRDIMM Gen2: Transforming HPC and AI in the Data Center

Built on TSMC's performance-enhanced N3P node, this live demo featured Cadence's latest high-speed DDR5 MRDIMM memory IP, operating at 12.8Gbps. This Gen2 solution delivers the bandwidth and low latency needed to meet the demands of modern datacenter workloads—supporting scalable performance for AI training, inference, and high-performance computing.

The Main Stage

Beyond the live demos, Cadence's presence at FMS 2025 extended to the main stage, where Cadence's Frank Ferro and Nidish Kamath from Rambus delivered an insightful presentation on the future of memory technologies. Their session drew a large audience and created buzz around DDR advancements and AI-driven memory architectures.

Cadence's Gautam Singampalli also took the stage with Maximizing AI Accelerator Performance with UALink: Advanced Features and Techniques, offering a deep dive into new methods for enhancing AI accelerator efficiency through UALink's advanced capabilities.

Looking Ahead

FMS 2025 provided an opportunity to share Cadence's cutting-edge memory and PCIe IP solutions with the memory and storage ecosystem. We're eager to continue discussions about how we can help address our customers' next-generation memory and high-speed interconnect challenges and partner to power AI and HPC innovation.

Learn more about our UALINK, UCIe, DDR5 MRDIMM, and PCIe 6.0 IP solutions.