Next-Gen Memory Starts Here: Cadence at the Future of Memory and Storage

FMS: the Future of Memory and Storage is fast approaching (August 5-7 at the Santa Clara Convention Center), and with it comes a unique opportunity to connect with some of the brightest minds in the semiconductor, memory, and storage industry. This premier event brings together industry experts, innovators, and leaders to highlight advancements shaping the future of memory and storage technology.

What to Expect in Our Booth

At this year's summit, Cadence will host live demonstrations of its innovative IP solutions, which are designed to solve complex challenges in memory design, performance optimization, and power efficiency.

First PCIe 6.0 IP Subsystem in Silicon

Problem it solves: As data center workloads scale, designers face increasing pressure to deliver higher bandwidth with lower power and tighter compliance margins. Traditional IP solutions often fall short in configurability and silicon validation.

Cadence's solution: Our PCIe 6.0 IP subsystem is not just compliant—it's silicon-proven, configurable, and optimized for low power. Drawing on Cadence's rich history of multi-lane subsystem testing, our PCIe 6.0 IP subsystem benefits from years of rigorous validation across diverse use cases—ensuring robust performance, seamless integration, and accelerated time to market. This demo highlights how our IP accelerates time to market while ensuring robust interoperability and performance.

DDR5 @ 12.8Gbps MRDIMM Gen2

Problem it solves: AI and HPC applications demand memory solutions that can keep up with massive throughput and latency requirements. Conventional DDR5 implementations struggle to scale efficiently.

Cadence's solution: Our DDR5 MRDIMM Gen2 IP delivers blazing-fast 12.8Gbps performance, enabling next-gen AI and HPC platforms to thrive. This demo illustrates how Cadence is pushing the boundaries of memory bandwidth while transforming HPC and AI in the data center.

Why You Should Visit Our Booth

Cadence is powered by some of the best minds in the industry. When you visit our booth, you'll have access to live consultations with experts ready to answer your toughest questions and help you uncover the right solutions for your design needs.

Whether you're designing for AI inference, training, or high-throughput networking, Cadence IP can help you meet aggressive performance targets without compromising power or compliance.

Our demos are backed by robust silicon validation, deep ecosystem partnerships, and a relentless focus on customer success. From PHY architecture to full subsystem integration, Cadence IP are the building blocks of AI. They include not only our industry-leading PCIe and memory subsystems, but also chiplet-ready architectures, Tensilica IP, and a full suite of design and integration services.

Let's Connect

Stop by Booth 1248 to meet our experts, see the demos in action, and explore how Cadence can help you solve your toughest design challenges. Can't make it in person? Visit our Cadence IP page to learn more.

I will also be presenting at the show—feel free to join my presentation:

• Topic: Maximizing AI Accelerator Performance with UALink: Advanced Features and Techniques
• When: Thursday, August 7, 2025 at 8:30am – 9:30am
• Room: NETC-301-1 Ballroom C (1st floor)

We look forward to seeing you in Santa Clara!