Advancing Die-to-Die Connectivity: The Next-Generation UCIe IP Subsystem

Transceiver Simulation with Full RC Extraction and 25mm Channel

In today’s evolving AI/ML and HPC/datacenter landscapes, die-to-die connectivity is essential for achieving high-performance and efficient data transfer. Cadence has achieved a significant milestone with the successful tapeout of its 32G UCIe standard package IP subsystem on TSMC’s 3nm (N3P) process technology. Designed to advance the performance, power efficiency, and integration of die-to-die connectivity, the subsystem features a comprehensive range of advanced capabilities, setting a new standard in ultra-fast, high-performance interconnect solutions. Building on seven years of expertise in die-to-die solutions and the success of our proprietary 16Gbps UCIe IP subsystem, this next-generation product delivers improved performance and flexibility while maintaining the reliability and precision proven by its predecessors. Like its 16G predecessor test vehicles, the entire subsystem is implemented in silicon with the ability to transfer data off-chip through high-speed I/Os. This setup enables a user to send real traffic using their SoC prototyped in FPGA and connect to our test board to develop and confirm the full software stack.

What’s New in Our Innovative 32G UCIe Solution?

• High-speed data transfer ranging from 4Gbps to 32Gbps: This IP supports all UCIe data transfer rates from 4Gbps to 32Gbps, offering flexibility across various customer applications. This broad speed support makes the IP ideal for diverse use cases, providing scalable performance to meet the requirements of both low-power systems and high-throughput systems.
• Advanced equalization for full range of channel reach at 32Gbps: The integrated equalization functionality allows the IP to support channels up to 25mm in length at 32Gbps, ensuring reliable performance even in extended or complex physical layouts. This capability enhances the flexibility and robustness of the system’s die-to-die interconnect.
• Optimized design for 32Gbps speed and wide interoperability: The design of the IP is optimized to operate seamlessly at the UCIe standard maximum speed of 32Gbps, ensuring robust interoperability with any UCIe solution. Optimizing to 32Gbps allows the best performance metrics and wider interoperability.
• Universal interoperability for various transmitter and receiver configurations: The UCIe transmitter of Cadence’s IP supports both half-rate and quad-rate UCIe receiver implementations, ensuring broad compatibility across various receiver configurations. With the ability to generate clocks up to 16GHz, this IP provides robust support for data rates up to 32Gbps, ensuring full interoperability in diverse UCIe applications.

Our 32G UCIe IP Continues the Following Key Features from Our 16G Solution

• Self-calibrating capabilities and hardware-based bring-up with no firmware requirements: The new 32G IP is fully UCIe compliant, just like the 16G design, ensuring seamless integration into existing UCIe ecosystems. A key feature of Cadence’s UCIe solutions has been their self-calibration functionality and hardware-based bring-up, which removes the need for any firmware intervention during system bring-up. This significantly simplifies the setup process by eliminating the need for firmware loading during the setup process. This functionality is a standard offering across our entire UCIe IP portfolio.
• At rate loopback for wafer sort and validation: The IP features at-rate loopback at 32Gbps, enabling efficient wafer sort, a key feature for D2D solutions, and simplifying packaged part validation. Additionally, the full die-to-die (D2D) loopback mode ensures comprehensive validation across the entire link, including the channel, from one die to its partner and back, offering complete testing coverage for high-reliability systems.
• Integrated internal PLL continues: Like all previous Cadence UCIe IPs, this IP includes an internal Phase-Locked Loop (PLL) that autonomously generates the necessary Lclk and high-speed clocks within the IP. The user only has to supply a 100MHz reference clock, with the option to provide the Lclk from the SOC. This allows for simplified clock management, streamlined integration, and reduced system complexity.
• Robust performance that supports operation condition extremes: Cadence’s UCIe IP solutions feature a “Maintenance Mode” that performs regular background runtime recalibration to ensure uninterrupted operation even under changing operation conditions, such as supply voltage and temperature, drifts in the system environment.
• Support for vendor-defined messaging over sideband links: The IP supports vendor-defined messages over sideband links, fully compliant with UCIe specifications. This feature ensures effective communication and control across the die-to-die interconnect, enhancing system integration. It is part of both the 16Gbps and 32Gbps version of our UCIe IP solutions.
• Wide protocol support: Cadence’s 32G UCIe IP also offers wide protocol support to enable pre-validated and high performance, low latency, and low power subsystems for any application.

Cadence's new 32G UCIe IP subsystem marks a major advancement in die-to-die connectivity. It offers high performance, power efficiency, and integration with a range of advanced capabilities. This next-generation solution maintains the reliability and precision of its predecessors while introducing features such as self-calibrating capabilities, hardware-based bring-up, and robust performance under varying conditions. As a contributing member of the UCIe consortium, Cadence is helping to shape the future of the chiplet ecosystem and meet the needs of modern high-performance computing, datacenters, and AI/ML applications. For more information or inquiries, please contact us to explore how our UCIe IP can support your projects.

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