How Cadence Is Expanding Innovation for 3D-IC Design

11 Jun 2024 • 5 minute read

The market is trending towards integrating and stacking multiple chiplets into a single package to meet the growing demands of speed, connectivity, and intelligence. However, designing and signing off chiplets and packages individually is time-consuming and inefficient. In addition to planning, and aligning the chip stack, standard design closure checks like timing and power signoff, the system-level effects such as thermal and mechanical stress must be considered. This is where the comprehensive Cadence Integrity 3D-IC platform comes in, with its unique features designed to address these system-level challenges that may impact individual chip design closure.

Cadence is continuously expanding the innovation for 3D-IC design through research partnerships. During the recent CadenceLive Silicon Valley, CT Kao, Product Engineering Director at Cadence, presented how the Cadence Integrity 3D-IC platform and partnerships are paving the way for improvements in the next-gen multi-chiplet design solution. This blog is an excerpt from a presentation at CadenceLive Silicon Valley, 2024. If you missed the chance to watch this presentation live, register to watch this and other 3D-IC/Chiplet presentations on the CadenceLIVE on-demand site.

3D-IC and Chiplet Challenges

When developing advanced package multi-die designs, engineers may encounter complexities in design analysis and flow, configuration challenges, and system-level thermal and power integrity issues.

Such issues arise from connectivity, corner explosion, and thermal analysis and may lead to extended design turnaround times. While the challenges in 3D-IC and Chiplet design are well understood, they are becoming more difficult to manage in leading-edge designs. Design teams spend more time writing scripts and customizing the flow for each design, leaving less time for actual design work. To address these challenges, the Cadence Integrity 3D-IC platform offers a comprehensive, unified solution and standards that simplify the multi-die design and implementation process. This significantly improves productivity and reduces design turnaround time.

Cadence Integrity 3D-IC Platform

Cadence Integrity 3D-IC platform is the industry’s only unified platform that includes system planning, packaging, and system-level analysis in a single cockpit. It is built around Cadence industry leading Innovus implementation system. It has an interface to co-design with analog dies using the Virtuoso environment and different types of packaging with Allegro X Advanced Package Designer.

These key components make the Integrity 3D-IC platform the first complete and integrated solution for optimizing multiple chiplets and enabling actual system-driven power performance and area (PPA) improvements for multi-chiplet designs.

Expanding Innovation in 3D-IC Design

Cadence is expanding its 3D-IC design platform through collaborations. It has recently added features such as improved viewing capabilities, 3D partitioning and early floor synthesis (EFS), Integrated What-if Thermal Analysis, and System-level analysis to the Integrity 3D-IC Platform. Additionally, the Integrity 3D-IC platform can now be used with the Clarity 3D solver to analyze signal integrity by selecting specific nets. It also includes SI/PI checks and the ability to generate waveforms and eye diagrams.

Enhanced Viewing Capabilities

With the enhanced viewing capabilities, the designers can have a 2D canvas from the top and a cross-section side-by-side view for their designs. Also, the Integrity 3D-IC platform enables designers to create a 3D stack view with fly-line connections, selected components, and objects to see the connection between the wire bound or all those bumps.

It also includes a back-annotation view from the thermal analysis and all those hotspots where temperature contours can be back-annotated into the design. This helps designers better understand and improve their designs.

3D Partitioning and Floor Plan Synthesis

The Integrity 3D-IC platform empowers designers with 3D partitioning and EFS. With these capabilities, designers can break down the two-die design into two connected die designs (top and bottom). This thermally aware floor synthesis can be done either at the block level and block-based or module-based and considers the number of I/O ports, wire lengths, and timing.

Integrated What-If Thermal Analysis

The integrated what-if analysis automatically analyzes the floorplan and helps decide how to rearrange and spread the high-density power blocks and reduce the temperature peak. For instance, using the power maps and what-if analysis in the floorplan on the left-hand side, it was possible to reduce the temperature peak by 15°C.

System Level Analysis

The flow manager helps perform the system-level analysis, enabling designers to perform power and thermal analyses. It includes Tempus for the timing analysis, Quantus for signoff, and Pegasus for DRC/LVS. Recently, Cadence included SI/PI in this flow. Designers using the Integrity 3D-IC platform can now do the handshaking with Clarity and top WB for signal integrity analysis by selecting interested nets.

It helps them with the EM analysis, S-parameter extraction and generating the waveform and Eye diagram through this schematic of the top WB.

Integrity 3D-IC integration with Thermal, Power, and SI/PI Analysis also offers many advantages at the foundry level. It has enabled foundries to perform early thermal and sign-off analyses using the Celsius thermal solver. Additionally, it enables them to perform Early rail analysis using a chip power model with Voltus and SI/PI analysis.

Integrity 3D-IC Platform: Benefits

Overall, the Integrity 3D-IC platform offers multiple benefits for the designers and foundries, such as

Modularity allows implementation analysis and signoff teams to work on the multi-chiplet designs concurrently.
A unified platform database allows a straightforward transfer of design information across the entire 3D-IC design flow.
Built-in flow manager provides tight integration with the Cadence analysis and signoff products for thermal power, EMIR, and static timing analysis.
Built to address the future trend of actual 3D stacks for partitioning and cross-die optimization.
The system planner helps reduce iterations and shorter cycle times.
Ensures the performance and performs the on-chip analysis for timing, power, DRC/LVS, signal integrity (SI), power integrity (PI), and thermal off-chip analysis.

Conclusion

Integrity 3D-IC platform is a systematic innovation for 3D-IC design, focusing on 2-D and 3-D implementation technology at the system level. The reference flows based on the Integrity 3D-IC platform offer key capabilities, including early analysis for the power delivery network (PDN), thermal and system-level layout versus schematic (LVS), and design rule checking (DRC). The flows also incorporate the Cadence AllegroX packaging technologies and multiphysics system-level analysis tools, Celsius Thermal Solver, and Clarity3D Solver, which provide further productivity benefits. The Early adopters and partners using this platform have witnessed the benefits such as:

32X difference in bandwidth as they move from 4channel (64bits) to 16 channels for 32bits.
Reduced area for 3 Die stacking.
Strong impact of L2 configuration on 2D PPA.
3D 2-dies (F2F) using concurrent 3D flow improved PPA compared to 2D.