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Digital Implementation
  • Neha Joshi
    Power Is HOT and Touches Everything and Everybody! But the Challenge Is To Deal With Low Power During Design Synthesis; How?
    By Neha Joshi | 10 May 2022
    Low-Power synthesis is one of the important stages in the full IC flow. Here, you synthesize the design from behavioral description to gates while optimizing for dynamic and leakage power using various techniques. We understand that it is not always easy to estimate power, but Cadence offers a solution in the form of a low-power synthesis flow with Genus. Are you interested in exploring: What the complete low-power...
    0 Comments
    Tags:
    Low Power | Genus | Digital Implementation | Synthesis | power optimization
  • Neha Joshi
    Are You Planning To Synthesize Your Design? Do You Want To Explore the Synthesis Flow in Genus Synthesis Solution?
    By Neha Joshi | 9 May 2022
    A Logic Synthesis is a process of optimizing the design's area, timing, and power. You might be a beginner in the synthesis world, but we can help you sail through it smoothly. It's time to introduce yourself to our tool for synthesis , Genus Synthesis Solution. The ultimate goal of the Cadence ® Genus Synthesis Solution is very simple: deliver the best possible productivity during register-transfer-level (RTL) design...
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    Tags:
    Genus | Flows | Logic Design | Optimize | Synthesis
  • Atreya
    Chris, Kris, Cris, Your Name, My Name; Does How You Spell the Name Matter to Conformal?
    By Atreya | 7 May 2022
    No matter how your name is spelt in different countries, and how they say it, once they get to know you, people identify you as the same person. Ah! this is Chris, Cris, Kris, Kirshner, or Krishna. And I know this dude, even though he has transformed since I last saw him, and is 10 years older than what I remember. Likewise, different tools have different ways of naming the same design object and the default rules...
    0 Comments
    Tags:
    conformal
  • Neha Joshi
    Do You Want to Explore Instances in Genus Synthesis Solution Layout GUI?
    By Neha Joshi | 6 May 2022
    What comes to your mind when we say Genus Layout GUI (Graphical User Interface)? You picture the floorplan filled with instances and objects. Imagine you need to highlight the specific instance or timing path in GUI? Do you think it’s tricky? Not at all!! Genus Synthesis Solution GUI (Graphical User Interface) helps you view and highlight the instances and timing results to better explore/debug your design. Now...
    0 Comments
    Tags:
    Genus | gui | place and route | highlighted objects | physical implementation
  • Nikhil Jatana
    Voltus Voice: Simplifying Power Signoff for HPC Systems: Super-Charge your Power Methodology with Event-Based Power Analysis
    By Nikhil Jatana | 20 Apr 2022
    In the first post of our " Simplifying Power Signoff for HPC Systems" blog series, we discuss how the Voltus event-based power analysis flow helps in making accurate power estimation for large scale and high-performance designs early in the development process.
    0 Comments
    Tags:
    Silicon Signoff and Verification | Voltus IC Power Integrity Solution | Power Signoff | Cycle Accurate Power Estimation | Event-Based Power Analysis | Power Analysis
  • VNelson
    Floorplanning Frustrations Got You Down? Help Is on the Way!
    By VNelson | 15 Apr 2022
    This post describes a channel of videos created to show how to floorplan a design using Innovus Implementation System software.
    0 Comments
    Tags:
    Floorplanning | Innovus
  • Vinod Khera
    Mitigating Congestion, CTS, OCV and Other Challenges using Cadence Tools and Support
    By Vinod Khera | 25 Mar 2022
    With the shrinking gemoetries and data-intensive endeavours of the upcoming industries like IoT, Robotics, Self-Driving Cars, 5G and 6G phones, designs are getting more complex. There are many challenges like congestion, routing, on-chip variations, and unconstrained paths that must be addressed. Cadence 24X7 support and rapid adoption kits (RAKs) helps customers by providing ready support and quick resolution.
    0 Comments
    Tags:
    debug | Routing | Unconstrained Path | congestion | OCV | SOCV | RAKs
  • Anshika Gahlaut
    Voltus Voice: Early Power and Thermal Integrity Analysis in 3D-ICs - Why it Really Matters?
    By Anshika Gahlaut | 11 Mar 2022
    Learn how to navigate through the challenges of power and thermal integrity analysis in 3D-ICs with the CadenceTECHTALK webinar on 23rd March, 2022.
    0 Comments
    Tags:
    Celsius Thermal Solver | system in package | Voltus IC Power Integrity Solution | Integrity 3D-IC Platform | 3D-IC | Power Integrity | Thermal Integrity | Multi-Chiplet Design
  • sharvey
    Voltus Voice: Hierarchical Power Integrity Analysis—Why xPGV Modeling Is the Designer's Best Choice for Mega-Sized Chips
    By sharvey | 1 Mar 2022
    In the final part of our "Hierarchical Power Integrity Analysis" blog series, we explore how to use the reduced xPGV models at the top level to improve chip design productivity.
    0 Comments
    Tags:
    Voltus XM | Silicon Signoff and Verification | Voltus IC Power Integrity Solution | xPGV models | Power Integrity | hierarchical power integrity analysis | IRdrop | Extreme Modeling | Full-Chip
  • Vinod Khera
    Adopting a Faster, More Efficient Path to Multi-Chiplet Design
    By Vinod Khera | 16 Feb 2022
    Gone are the days when process shrinking was considered as the primary driver of product innovation and improved system performance. The path most are taking leads to the world of “More than Moore.” Vertical Stacking of heterogeneous chips and chiplets is the name of the game . It will have a significant impact on applications that require ultra-high-performance and low power, such as multi-core CPUs, GPUs, packet...
    0 Comments
    Tags:
    chiplets | 3D-IC | Integrity | Thermal Integrity | system planning | Multi-Chiplet Design
  • Neha Joshi
    Is your Compression Technique Unified? Wanna Explore?
    By Neha Joshi | 26 Jan 2022
    Scan compression is critical for addressing the rapid rise of test costs without sacrificing coverage requirements. Although it has been widely adopted, it has its limitations. In today's era demand is not just high coverage but also the ability to verify that the design is working in the field. A unified compression is an approach that unifies scan compression and logic built-in self-test (LBIST). It leverages physically...
    0 Comments
    Tags:
    scan | DFT | compression | Genus | Synthesis
  • Priya E Joseph
    Voltus Voice: Playback 2021 - Power Integrity Blogs At a Glance
    By Priya E Joseph | 23 Dec 2021
    A recap of the power integrity posts in the Voltus Voice blog series through 2021.
    0 Comments
    Tags:
    Silicon Signoff and Verification | Voltus IC Power Integrity Solution | electrostatic discharge | resistance analysis | hierarchical power integrity analysis | Digital Implementation | rush current analysis
  • Anshika Gahlaut
    Voltus Voice: ESD Analysis Task Assistant: Your Key to 'Getting Started'
    By Anshika Gahlaut | 9 Dec 2021
    This blog discusses the implementation of task assistant for the Voltus ESD analysis flow. ESD task assistant is an in-tool help access medium that facilitates the quick resolution of your ESD questions.
    0 Comments
    Tags:
    Silicon Signoff and Verification | Voltus IC Power Integrity Solution | ESD reports | Power Signoff | electrostatic discharge | current density | Power Integrity | ESD
  • sharvey
    Voltus Voice: Hierarchical Power Integrity Analysis—Everything You Need to Know About PI Analysis
    By sharvey | 8 Nov 2021
    In part 2 of our "Hierarchical Power Integrity Analysis" blog series, we discuss how to implement the hierarchical power integrity solution to create xPGV models of the IP blocks.
    0 Comments
    Tags:
    Voltus XM | Silicon Signoff and Verification | Voltus IC Power Integrity Solution | xPGV models | Power Integrity | hierarchical power integrity analysis | IRdrop | Extreme Modeling | Full-Chip
  • Priya E Joseph
    Voltus Voice: 6 Tips to Jump-start Your Voltus Stylus Migration Journey
    By Priya E Joseph | 22 Oct 2021
    Cadence Stylus UI streamlines the RTL-to-Signoff design flow, bringing all the Cadence digital synthesis and implementation tools together with ease. This blog shares tips to seamlessly migrate your Voltus legacy flows to Stylus UI.
    0 Comments
    Tags:
    Voltus IC Power Integrity Solution | Tempus | Signoff Analysis | Digital Implementation | Innovus | stylus
  • Neha Joshi
    Do you want to Flaunt your Expertise? Grab the Digital Badge Today!
    By Neha Joshi | 20 Sep 2021
    When you achieve the credit for proficiency, do you want to show it to the world? We know it isn’t easy to carry the actual physical badge (certificate) everywhere today. Why? Expenses, pandemic, making a list where to travel, to whom to show etc. Don’t worry! We have an easy and cost-free solution for this. Become Cadence Certified with Digital Badges. How? We have introduced courses for Digital Badge Exams for...
    0 Comments
    Tags:
    Genus | exam | badge | Joules | Synthesis
  • Rajat Chaudhry
    Voltus Voice: Hierarchical Power Integrity Analysis—The Quest for Accelerating Power Signoff in Extremely Large Designs
    By Rajat Chaudhry | 1 Sep 2021
    To help you tackle contemporary challenges related to extremely large design power signoff, the Voltus XM technology provides fast, accurate, and memory efficient analysis. Click here to know more.
    0 Comments
    Tags:
    Voltus XM | Silicon Signoff and Verification | Voltus IC Power Integrity Solution | xPGV models | Power Integrity | hierarchical power integrity analysis | IR drop | Extreme Modeling | Full-Chip
  • Neha Joshi
    Glitch?? Do Not Let It Impact Your Design Power!!
    By Neha Joshi | 11 Aug 2021
    A glitch, although, is an unnecessary signal transition in your design. But its impact can be tremendous. And yes, glitch contributes to glitch power as well. It can affect the power dissipation by many folds as it could be a significant part of your dynamic power consumption. So even though it is unnecessary but you must identify the glitch power!! How to analyze glitch power? Relax!! And leave glitch for Joules...
    0 Comments
    Tags:
    Low Power | RTL | Joules | glitch | Power Analysis | power optimization
  • Atreya
    Conformal Low Power Verification
    By Atreya | 9 Aug 2021
    Learn to verify low-power designs using Conformal ® Low-Power Verification. We've added a few super short videos in this channel to help you get going: Conformal Verify CPF Flow Graphical Interface Introduction Conformal Low Power Verify CPF Rule Filtering Here is the course to take you a little more in-depth into the concepts and techniques used for such verification: Conformal Low Power Verification ...
    0 Comments
  • bertrandgenneret
    Voltus Voice: Full-Chip Resistance Analysis – The Holy Grail of Power Grid Verification
    By bertrandgenneret | 16 Jul 2021
    Do you want to determine the weak spots in your power grid network at the start of physical design? Then go ahead and read this blog to learn more about the different resistance analysis techniques to prevent a voltage drop and model a robust power grid.
    0 Comments
    Tags:
    Silicon Signoff and Verification | Voltus IC Power Integrity Solution | power grid | Least-Resistive Path | Power Integrity | resistance analysis | IR drop | Full-Chip
  • VNelson
    Three Quick Ways to Get Up to Speed with Innovus 21.1 with Stylus Common UI
    By VNelson | 7 Jul 2021
    Hello Digital Designers, Innovus 21.1 released a few weeks ago and you might be curious about what’s new and improved in the tool. Here are three quick ways to get up to speed: Watch the short demo of the Innovus 21.1 GUI that I captured to provide an overview of the user interface. If you already use Innovus, I would recommend my go-to source, created by our Pubs team, What’s New in Innovus Stylus Common UI...
    0 Comments
    Tags:
    place and route | Digital Implementation | Innovus
  • Priya E Joseph
    Voltus Voice: Unleashing the Power of Intelligent System Design Strategy - A chat with Rajat Chaudhry
    By Priya E Joseph | 15 Jun 2021
    In this blog, Rajat Chaudhry (Product Management Director of Voltus) tells us how Voltus has introduced several innovative technologies to address power signoff challenges, while integrating seamlessly with Cadence IC, package, PCB, and system tools.
    0 Comments
    Tags:
    Innovus Power Integrity | Silicon Signoff and Verification | Voltus IC Power Integrity Solution | hierarchical power integrity analysis | Digital Implementation | Multiphysics System Analysis | Tempus Power Integrity
  • Neha Joshi
    Have You Encountered Any Error/Warning During Scan Insertion in Genus? Do You Want to Resolve It?
    By Neha Joshi | 14 Jun 2021
    Design for Test (DFT) techniques provide measures to test the manufactured device for quality and coverage comprehensively. You might encounter Error or Warning messages while inserting scan during the synthesis stage. We know it is a little tricky to resolve DFT Errors and Warning. But don't worry!! We can help provide guidance. For example, the Error or Warning could be related to checking DFT rules, reporting, defining...
    0 Comments
    Tags:
    scan | DFT | Genus | warning | error
  • Vijetha
    Voltus Voice: Demystifying ESD—Charting Your Way through Voltus ESD Reports
    By Vijetha | 28 May 2021
    In the concluding blog of our "Demystifying ESD" series, we walk you through the features of the Voltus Electrostatic Discharge (ESD) analysis reports that provide a clear insight on your design's vulnerability to ESD, from the early-design phase to tapeout.
    0 Comments
    Tags:
    Silicon Signoff and Verification | electromigration | Voltus IC Power Integrity Solution | ESD reports | electrostatic discharge | current density | Power Integrity | Innovus | clamp | bump
  • Neha Joshi
    Do You Know DFT Violations Can Be Debugged Using Genus GUI? Excited to Explore?
    By Neha Joshi | 12 May 2021
    Design for Test (DFT) techniques provide measures to comprehensively test the manufactured device for quality and coverage. During the synthesis stage, you might encounter DFT violations that need to be resolved. We know it is a complicated process to debug the DFT violations. But don’t worry!! We can help you to sail through this. Check the DFT Analyzer capability, which helps in graphical debugging of DFT violations...
    0 Comments
    Tags:
    scan | DFT | Genus | gui | debug | Digital Implementation | Violations | Synthesis
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