Digital Design (Digital Full-Flow and Signoff) Blogs

Learn how the Voltus-Sigrity X integrated solution can help you achieve faster system-level power integrity analysis and closure.

How to fix the bugs after RTL freeze and perform ECO. Learn how Automated ECO Implementation using Conformal ECO Designer helped them to automate their pre-mask ECOs implementation and complete it in 645 –730sec only.

This webinar encourages you to learn and apply the latest innovations in the Cadence®︎ Tempus Timing Solution SSV221 Release.

Artificial Intelligence (AI) plays a key role in semiconductors to meet the challenging demand and rising customer expectations. But implementing these AI models in Hardware (FPGA) is challenging. AI developers generally use TensorFlow/Caffe model, w...

Vector profiling enables ASIC designers to quickly identify areas with maximum activity and power consumption when analyzing long simulation vectors, accelerating power signoff of billion-node designs. Focusing on meaningful events reduce the power signoff analysis runtime and memory usage drastically, having a direct impact on time-to-market. Check out this blog to know more.

Are you passionate about cooking? Err... Don't think it is a regular cooking class.

Here we tend to cook cooler power solutions! 

Do you know creating a cooler IC chip is as easy as enjoying the ice-cream in summer to beat the heat? 

Low-Power synthesis is one of the important stages in the full IC flow. Using various techniques, you synthesize the design from behavioral description to gates while optimizing for dynamic…

Physical design challenges such as congestion, routing, on-chip variation (OCV), and unconstrained paths are significant issues in achieving the design goals. Managing the routing congestion and physical design challenges with the least amount of effort is a big problem for physical design engineers. Further, the usage of advanced nodes and increasing functionality over SoC is leading to rising complexity and conflicting…

This blog shares five great features to unlock the potential of your digital designs and enhance full-chip power signoff.

The Silicon Signoff and Verification (SSV) 22.1 release is now available for download.

This blog post describes the phenomenon of Aging, the factors affecting it, and how Cadence solves this problem with its groundbreaking Aging-Aware STA technology enabled using Liberate, Spectre, and Tempus STA.

No matter how you feel about the topic, we're definitely past the turning point in history where most humans interact with machines much more than other humans.

Advancements in artificial intelligence and machine learning (AI/ML) have helped us develop immensely useful and sometimes just-for-fun applications including image creations with AI inputs.

Look at these images generated from text for example, with some weights…

Passion motivates and helps you pursue it further, but gaining expertise requires time and effort. For example, photography is a popular hobby because anyone can take a picture. But to gain expertise requires time and effort to experiment with various techniques to improve your skills.                                                                                                                                                                                                                                                                      

Leveraging Cadence Cerberus AI-Enabled Chip Optimization Solution MediaTek Achieves Transformative PPA and Improved Productivity

The semiconductor industry is in the midst of a global renaissance. With the advent of technologies like 5G, autonomous driving, hyperscale compute, and the Internet of things, there has been an explosion in demand for electronics. Consumers want chips that must have more functionality, more…

This blog post mentions the Cadence Low Power Solution, a design-to-signoff methodology, that helps you implement several low-power techniques to reduce both dynamic and leakage power during synthesis and design implementation. Formal verification can be run to ensure the functionality of a low-power design.

This post facilitates easy access to the Voltus Help and Documentation through the most useful resources from the Cadence support and corporate websites directly from the tool interface.

We all look for 100% perfection and want to turn our dreams (expectations) into reality as far as we can. Are you also looking for a magic wand to turn expectation into reality?

The story applies to DFT world too!! Design for Test (DFT) techniques comprehensively provide measures to test the manufactured device for quality and coverage. We expect 100% coverage and fault testing.

And the hard work for the design starts…

Low-Power synthesis is one of the important stages in the full IC flow. Here, you synthesize the design from behavioral description to gates while optimizing for dynamic and leakage power using various techniques. We understand that it is not always easy to estimate power, but Cadence offers a solution in the form of a low-power synthesis flow with Genus.

Are you interested in exploring:

• What the complete low-power synthesis…

A Logic Synthesis is a process of optimizing the design's area, timing, and power.

You might be a beginner in the synthesis world, but we can help you sail through it smoothly. It's time to introduce yourself to our tool for synthesis, Genus Synthesis Solution.

The ultimate goal of the Cadence^® Genus  Synthesis Solution is very simple: deliver the best possible productivity during register-transfer-level (RTL…

No matter how your name is spelt in different countries, and how they say it, once they get to know you, people identify you as the same person.

Ah! this is Chris, Cris, Kris, Kirshner, or Krishna. And I know this dude, even though he has transformed since I last saw him, and is 10 years older than what I remember. 

Likewise, different tools have different ways of naming the same design object and the default rules rarely…

What comes to your mind when we say Genus Layout GUI (Graphical User Interface)? You picture the floorplan filled with instances and objects. Imagine you need to highlight the specific instance or timing path in GUI?

Do you think it’s tricky? Not at all!!

Genus Synthesis Solution GUI (Graphical User Interface) helps you view and highlight the instances and timing results to better explore/debug your design.

Now think…

In the first post of our " Simplifying Power Signoff for HPC Systems" blog series, we discuss how the Voltus event-based power analysis flow helps in making accurate power estimation for large scale and high-performance designs early in the development process.

This post describes a channel of videos created to show how to floorplan a design using Innovus Implementation System software.

With the shrinking gemoetries and data-intensive endeavours of the upcoming industries like IoT, Robotics, Self-Driving Cars, 5G and 6G phones, designs are getting more complex. There are many challenges like congestion, routing, on-chip variations, and unconstrained paths that must be addressed. Cadence 24X7 support and rapid adoption kits (RAKs) helps customers by providing ready support and quick resolution.

Learn how to navigate through the challenges of power and thermal integrity analysis in 3D-ICs with the CadenceTECHTALK webinar on 23rd March, 2022.

In the final part of our "Hierarchical Power Integrity Analysis" blog series, we explore how to use the reduced xPGV models at the top level to improve chip design productivity.