Digital Implementation Blogs

Timing closure is one of the most crucial steps of a digital design. Therefore, to meet timing at the later stages of design signoff, it is imperative to consider timing analysis within the synthesis stage. We know real designs are complex, and so is the timing analysis. Unfortunately, we cannot reduce the complexity, but we can make the ride smooth during the timing analysis journey!! The trick is to use a GUI-based...

Hello Digital Designers, Interested in learning more about how to implement a low-power design? Do you have multiple voltage islands that need level-shifting, and isolation, and also require a CPF or !EEE 1801 power intent definition file? Do you need to reduce leakage and dynamic power? We have just released several training videos that can answer many of your low-power questions. The newly released videos...

This blog discusses the different Voltus electrostatic discharge (ESD) checks in the form of rules to ensure your design is protected against ESD.

You put your design through a multitude of tools for various transformations. Going back to formal verification in between every change to rely on your simulation tools can be a rigorous approach, but wait... there is an easier way: Use equivalence checking, with Conformal® Equivalence Checker. And that easier way is made even easier with these videos on how to do your equivalence checking, along with a few of...

Do you have a requirement to specify measurements that are not default while performing memory characterization? Liberate MX has a solution for you.

With advanced-process nodes, a standard cell's physical delay, net delay, and congestion all lead to a higher netlist requirement. Genus/Innovus iSpatial bridges synthesis and implementation with integrated core engines and unified physical optim...

This blog post outlines four simple steps for analysis of your electrostatic discharge (ESD) protection circuitry using the Voltus ESD Analysis solution.

The hustle bustle of the cities is only an example of the external noise, which we are aware of through the obvious observations of our sensory organs. However, in terms of electronics, a noise maybe defined as any kind of unwanted signal that interferes with the real signal in a timing path in a cell or circuit. Modeling of accurate noise characteristics at the cell level and being aware of the possible failures early...

Hi everyone, Are you interested in reducing the power dissipation of your design? Who wouldn’t? What about taking the advantage of Clock Gating? Clock Gating is a technique that enables inactive clocked elements to have gating logic automatical...

A blog on how the Voltus power-gating analysis solution enables engineers to address the low-power design challenge of extending battery life while reducing the leakage power.

Ever wondered what should you do if any arc, cell, or PVTs failed in a characterization run? Do you need to rerun the entire characterization process? Certainly not if you know about how to use the recovery workflow in the multi-PVT characterization flow! Read more...

"How many tape-outs have you done?" asked the design manager of a semiconductor company. My colleague and I were on a call with him to walk him through an implementation training agenda. He further explained the intent of the question “I am looking for trainer who has hands-on experience in implementing design. I want the training to be more design challenge oriented rather than just talking about command and switches...

Voltus TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy...

Hi everyone, Searching for yet another method to improve the QoR of your design? What about taking advantage of the improvements in area and power that the Multibit Cell Inferencing (MBCI) flow provides? Merging to multibit cells refers to the merging of the individual register bits from the same or different bus into multibit cell instances. That way, a single clock pin can be used to trigger all register bits in...

This year all our “regular” routines were shaken up by COVID-19, which brought along many challenges for people all over the world.

We just recently released a training course that we are excited to tell you about. The course is RTL-to-GDSII Flow . This course is unique in that it takes a tiny design through a wide variety of Cadence tools so that you can gain some exposure to tools that you may not be familiar with. You learn how to implement a design from RTL-to-GDSII using Cadence tools. You will start by learning how to code a design in...

This blog highlights the key capabilities of the Voltus Self-Heat Effect (SHE) analysis flow.

To arrive at your targeted and optimized PPA, you will need to execute several Innovus runs with a variety of design parameters, commands, and options. You will then need to analyze the data which could mean wading through several log files and timing reports, a time-consuming task at best. To make it easier to visualize the data by generating an easy-to-read dashboard, Innovus now has integrated metrics commands...

This blog provides a summary of the last five blogs posted in the Library Characterization Tidbits blog series.

This blog introduces the new cloud-ready Extensively Parallel (XP) solution from Voltus IC Power Integrity Solution that allows designers to analyze massive designs in record time, distributing tasks among thousands of CPUs while seamlessly processing terabytes of data.

This is the second edition of the Library Characterization Tidbits' mini-series that shares insights into the questions that our customers frequently ask. Here, we continue with Part 2 of questions related to installation, configuration, and licensing of the Cadence Liberate Characterization solution.

This blog is in continuation with the post on the IR-Aware placement technology that is used at the early design stage to mitigate IR drop hotspots and ease final signoff. The second part of this blog discusses targeted PG stripes addition, another IR drop-centric technology to localize and remove the remaining hotspots.

In this blog, I will talk about the minimum period arc, which is a critical arc associated with the clock of a memory instance.

Power is HOT and it touches everything and everybody! But we can help with power analysis for your chip!! Do you want to: Sneak peek inside the schematic? Analyze power for various blocks? Identify the relation of hot cells with RTL? Explore annotation settings? Joules RTL Power Solution GUI (Graphical User Interface) helps you to analyze/debug the power estimation/results using several GUI capabilities...

Technology is changing the strategies we use to do things - oh so fast that 2010 seems like a distant past- within many spaces -- including the way we do our current topic of interest - Timing Signoff in Digital Implementation. The smaller nodes - le...