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2017 Annual HLS Survey Results

By Dave Pursley | 6 Jun 2017

As many of you know, Cadence (more correctly, “I”) recently performed an industry survey about HLS (High Level Synthesis) to get a fuller view of the productivity experiences and expectations from users and non-users alike. With nearly 200 responses, roughly half from HLS users and half not, we got a representative picture of what HLS users, potential users, and even skeptics believe about HLS. So let’s...

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High-Level Synthesis | survey | Stratus | HLS
Designing for Low Power… Begin at the Beginning

By Dave Pursley | 1 May 2017

So you have your RTL written, and it’s time to optimize to reduce power. If that’s your plan, you are likely leaving power on the table. It’s not that you can’t get a lot of savings with existing RTL synthesis tools (you certainly can!), but the biggest bang for the buck comes from early design decisions. Next time… start sooner! In fact, experts (not me, real experts ) estimate that...

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Low Power | high level synthesis | power | HLS
“Great” Hardware Design in a Wireless World

By Dave Pursley | 5 Apr 2017

As part three of the “ Making Hardware Design Great Again” series , let’s see how high-level synthesis (HLS) is helping designers create SoCs for WiFi, Bluetooth, and 5G. A common challenge in all three wireless spaces is that their standards are evolving… rapidly. Each new specification, or sub-specification, opens new opportunities. It’s a good opportunity for companies to establish...

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High-Level Synthesis | digital implementation | Digital Implementation | HLS
Making Hardware Design Great Again in 2017 - Part Deux

By Dave Pursley | 28 Feb 2017

In part one of this series, we talked about the role of the hardware designer , specifically comparing the ideal version of the hardware designer with the real-world version. From the emails I received, this is a bittersweet reality for many readers of this blog. Today, we will revisit the life of a hardware designer whose company, like most of the leading semiconductor companies, is using a hardware design paradigm...

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High-Level Synthesis | digital implementation | Digital Implementation | HLS
Making Hardware Design Great Again in 2017

By Dave Pursley | 22 Feb 2017

Ok, I admit it… that title is a blatant attempt to grab your attention. But it should also make you think. As a hardware designer, is your job great? Is it what you thought you’d be doing when you decided to become a designer? Is it, dare I say, fun? Or, like I hear so many times especially from those designing embedded integrated circuits , are you too bogged down in the muck of cranking out hardware...

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High-Level Synthesis | digital implementation | Digital Implementation | HLS
Five-Minute Tutorial: Innovus Clock Tree Synthesis and Debugger

By Kari | 21 Aug 2015

Hi Everyone, Last time, our Five-Minute Tutorial focused on the new Innovus Placement Optimization . The next step in the flow would be inserting clock trees. Now that we can take advantage of the CCOpt engine to create clock trees, we can also concurrently optimize for timing. But you still have the choice of whether or not to do so. This is a decision that could be design-dependent, and you may want to try both methods...

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training | ccopt | clock tree synthesis | debugger | Digital Implementation | Innovus
Five-Minute Tutorial: Innovus Placement Optimization

By Kari | 26 Jun 2015

Hi Everyone, Last time we got a quick look at The Innovus Standard Flow . Now I'd like to show you a bit more detail about some of the major steps. One of the new concepts in Innovus is how placement and pre-CTS timing optimization are now combined and interleaved. The GigaPlace placement engine is also new, and you will learn about its features. Click below to play the video (you'll need an active support...

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GigaPlace | Timing Optimization | Innovus | Placement
Five-Minute Tutorial: The Innovus Standard Flow

By Kari | 8 Jun 2015

Hi Everyone, Last week I highlighted a video featuring Innovus User Interface Tips . Now that you know how to get around, what next? Innovus has a new, more streamlined design flow. Most designs should start with what's called the Standard Flow. There is a great document on support.cadence.com outlining this flow. I found it very interesting, and I can't wait to try it on my next design. You'll need an...

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design flow | Digital Implementation | Innovus | five minute tutorial
Five-Minute Tutorial: Innovus User Interface Tips

By Kari | 2 Jun 2015

Hi Everyone, No doubt by now you have heard about the Innovus Implementation System , our next-generation physical implementation solution. It's always a bit scary to move to a new tool, but let me assure you that if you are a current Encounter user, you will be able to get around just fine in the Innovus system. A lot of the user interface will look very familiar to you, but there are some important changes and...

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UI | Digital Implementation | Innovus | five minute tutorial
Five-Minute Tutorial: Inserting Column Power Switches in EDI

By Kari | 20 Feb 2015

Hello my fellow Digital Designers, I'm sorry I haven't been around the blogs much lately. We've had a lot of exciting design work going on that has kept me pretty busy. I hope all of you are having a great 2015 so far. Just a heads up - all links below require a Cadence Online Support account. Our Educational Services team has been busy putting together some short videos called Training Bytes. These...

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EDI | Low Power | electronic system design | Cadence Online Support | Encounter Digital Implementation | five minute tutorial | power switch
Five-Minute Tutorial: One More Look at EM Models

By Kari | 20 Oct 2014

Just when you thought you were done setting up EM model files, along came another advanced node with more complicated rules. Sound familiar? I've already posted two Five-Minute Tutorials about EM Model File creation—you can review them here and here —but I need to post one more. In the more recent of the two previous posts, we ended up having to do some hand-editing. Raise your hand if you like to hand...

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Voltus | Digital Implementation | Power Analysis | EM | five minute tutorial
New Training Class: Get Up to Speed Fast When Migrating to Encounter Digital Implementation System

By wally1 | 11 Sep 2014

One question we often hear from experienced physical design engineers migrating to Encounter Digital Implementation System is, "How do I get up to speed on the tool as quickly as possible?" They understand place-and-route (P&R) concepts so they often don't need to attend a full training class over several days. Frequently, they may utilize Rapid Adoption Kits (RAKs), documentation, and other material...

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P&R | encounter digital implementation system | place and route | Rapid Adoption Kits | RAKs | physical implementation
Sharing is Learning - New RAKs and Videos for Digital Users on Cadence Support

By MJ Cad | 14 Apr 2014

Friends, you would probably agree that sharing knowledge is a practical way to solve business problems, and contributes to business goals. Thought I'd share some great content that I came across while navigating through https://support.cadence.com/ Rapid Adoption Kits: Static Timing Analysis using Tempus (Signoff Timing Analysis) 13.2 With the help of this RAK (rapid adoption kit) you will learn how to perform static...

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EDI | Encounterer Digital Implementation System | Digital Implementation forums | Tempus | EDI system | Cadence Online Support | digital implementation | Digital Implementation | Encounter Digital Implementation | signoff | timing signoff
Five-Minute Tutorial: Start the New Year with Voltus

By Kari | 9 Jan 2014

Happy New Year to all of our Digital Implementation Blog readers - and also to anyone new who is stopping by to check us out. We're glad you're here and we hope you'll hang out with us for a while! I thought we could start this new year with one of Cadence's newest tools: Voltus IC Power Integrity Solution. You can read all the official details in this news article , but if you're a digital designer...

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voltagestorm | vstorm | rail analysis | EPS | vector-based | Voltus | IRdrop | power grid view | Power Analysis | EM | vectorless | five minute tutorial | power | RAKs | power grid library
11 Things I Learned by Browsing Cadence Online Support

By MJ Cad | 14 Nov 2013

I guess by now most of us are already familiar with Rapid Adoption Kits (RAKs). These are packages that include a detailed instructional document and a lab database. You can browse all the available materials at https://support.cadence.com/ . Rapid Adoption Kits (RAKs) - The purpose of RAKs is to demonstrate how users can use Cadence tools in their design flows to improve productivity and to maximize the benefits of...

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Digital Implementation forums | How To | Cadence EDI System | power routing | Floorplanning | encounter digital implementation system | beginner | NanoRoute | training | Appnotes | Top Ten | digital implementation | Cadence Encounter Power System | GigaOpt | Digital Implementation | Encounter Digital Implementation | crosstalk | app notes | high performance | Rapid Adoption Kits | encounter power system | OpenAccess | Floorplanning and Prototyping | RAKs | FlipChip
Five-Minute Tutorial: EM Model Files Revisited

By Kari | 18 Sep 2013

Back in January, I posted a Five-Minute Tutorial about creating EM Model files . We'll be referencing this previous post a lot, so check it out quickly right now. That method has worked well for me, but on my most recent project, I hit some snags. As process nodes evolve, the EM models are becoming more complex, and translation scripts are not able to handle all of the cases. So, I had to dig back in and find a...

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EDI | qrcTechFile | EM Model | ICT | Techgen | iRCX | EPS | digital implementation | EM Model File | Power Analysis | EM | five minute tutorial
Answers to Top 10 Questions on Performing ECOs in EDI System

By wally1 | 17 Apr 2013

Applying ECOs to a design can be complex, stressful and error prone so it's important to apply the right tools and flow to implement the changes successfully. EDI System provides multiple ECO flows to physically implement ECOs efficiently and accurately based on your design requirements. And adding a tool such as Encounter Conformal ECO Designer or the Encounter Timing System's MMMC Signoff ECO capability can...

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ECO | Cadence EDI System | LEC | encounter digital implementation system | tips and tricks | Synthesis | mmmc
Five-Minute Tutorial: Set Flip-Chip Bumps as Voltage Sources in EPS/EDI Rail Analysis

By Kari | 26 Mar 2013

When running power and rail analysis for a flip chip, we used to have to spend some time creating the voltage sources. It wasn't too terrible; usually we would output the bumps into a Cadence Encounter Digital Implementation (EDI) .io file, then use a perl script to filter out the pwr/gnd bumps and create the voltage source file format. The script would need a bit of editing from project to project, but nothing too...

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EDI | rail analysis | EPS | Five-Minute tutorial | Power Analysis | flip chip | bump
CDNLive High-Performance Track: Do You Have What it Takes to Get Your High-Performance SoC to Market?

By Vasu Madabushi | 10 Mar 2013

Implementing SoCs with embedded processors at advanced nodes has become increasingly difficult. This is due to the complexity of the design functionality as well as the low power and increased performance requirements driven by a plethora of end-user applications in modern hand-held devices. Path-breaking trends in ARMv8 64-bit processor based microservers for power efficient cloud computing/data centers and high-end...

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ARMv8 | EDI | Low Power | Cortex-A15 | CDNLive | Cortex-A57 | Cortex-A7 | RC-Physical | NVIDIA | Avago | SoC | ccopt | digital | GigaOpt | Digital Implementation | Encounter Digital Implementation | AppliedMicro | high performance | CDNLive Silicon Valley | ARM | CDNLive! Cadence
Five-Minute Tutorial: Create Encounter Power System (EPS) Power-Grid Views For Standard Cells

By Kari | 22 Feb 2013

In today's tutorial, I'm giving you a sample EPS (Encounter Power System) script that you can use to generate power-grid views for your standard cells. Power-grid views are used during rail analysis, with IR-Drop and EM (electromigration/current density) being the two most popular analysis types. First, the LEF information is read in. The technology LEF needs to be read in first, then the LEF files of your...

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power-grid views | Low Power | rail analysis | current density | LEF | EPS | standard cells | Digital Implementation | qrc | Power Analysis | signoff | EM | IR drop | five minute tutorial | encounter power system | power
Quick Reference - 8 Ways to Optimize Power Using Encounter Digital Implementation (EDI) System

By MJ Cad | 12 Feb 2013

Everyone knows that the increasing speed and complexity of today's designs implies a significant increase in power consumption, which demands better optimization of your design for power. I am sure lot of us must be scratching our heads over how to achieve this, knowing that manual power optimization would be hopelessly slow and all too likely to contain errors. Here are 8 Top Things you need to know to optimize your...

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EDI | EDI system | Vt partition | low power tips | leakage | Jaiswal | EDI 11.1 | 8 ways | encounter digital implementation system | Encounter Digital Implementation | optLeakagePower | Leakage Optimization | power optimization | EDI 11 | dynamic power
Five-Minute Tutorial: Creating An EM Model File

By Kari | 14 Jan 2013

One of the least-fun parts of running power and rail analysis has always been coming up with the electromigration (EM) model file. In the past, this involved cracking open the process design rule manual, finding the appropriate equations, and creating a spreadsheet to calculate all the numbers needed for the various metal width and via sizes. Then, this information had to be put in the format of the model file used by...

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TAGS:

EDI | electromigration | rail analysis | EM Model | ICT | iRCX | EPS | Power Analysis | five minute tutorial
SPICE Correlation Made Easy by Encounter Timing System (ETS)

By MJ Cad | 10 Dec 2012

Hello, and welcome to my first blog! As an application engineer in customer support, I have received quite a few queries on how to do SPICE correlation of timing numbers. This blog is intended to help users understand the flow/methodology for doing SPICE correlation of static timing analysis (STA) timing results using Encounter Timing System (ETS). As we know, users do correlation of the critical paths in timing analysis...

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app note | Static timing analysis | ets | mukesh | STA | spice correlation | Spectre | signoff | ETS create_spice_deck | Encounter Timing System | SPICE
The Case for the Tiny Testcase

By Robert Dwyer | 16 Nov 2012

I often joke with customers that, although I realize they have to work on large designs, I do my best work on designs with just 2 or 3 instances. That's because I'm often trying to replicate an issue they've observed on their design and I'm attempting to reproduce that behavior in a smaller circuit. I've found tiny testcases to be extremely efficient ways to gain quick clarity on tool behaviors which...

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debug | tiny testcase | testcase | Test | encounter | Digital Implementation | small testcase | test case | Bob Dwyer | verification
Transitioning Your LEF-Based EDI System Design Flow to OpenAccess

By wally1 | 12 Nov 2012

The trend of combining analog and digital circuits on a single chip has been growing for several years. More recently I'm seeing more and more designers improve their productivity by transitioning their designs to Open Access (OA) and taking advantage of the interoperability between Virtuoso and the Encounter Digital Implementation (EDI) System. Whether you're performing floorplanning in Virtuoso (schematic-driven...

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EDI system | LEF | Cadence Online Support | Mixed-Signal | encounter | Virtuoso | oa | Digital Implementation | PDK | mixed signal | LEF to OpenAccess | Brian Wallace | OpenAccess | blog

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