Digital Implementation Blogs

To arrive at your targeted and optimized PPA, you will need to execute several Innovus runs with a variety of design parameters, commands, and options. You will then need to analyze the data which could mean wading through several log files and timing reports, a time-consuming task at best. To make it easier to visualize the data by generating an easy-to-read dashboard, Innovus now has integrated metrics commands...

This blog provides a summary of the last five blogs posted in the Library Characterization Tidbits blog series.

This blog introduces the new cloud-ready Extensively Parallel (XP) solution from Voltus IC Power Integrity Solution that allows designers to analyze massive designs in record time, distributing tasks among thousands of CPUs while seamlessly processing terabytes of data.

This is the second edition of the Library Characterization Tidbits' mini-series that shares insights into the questions that our customers frequently ask. Here, we continue with Part 2 of questions related to installation, configuration, and licensing of the Cadence Liberate Characterization solution.

This blog is in continuation with the post on the IR-Aware placement technology that is used at the early design stage to mitigate IR drop hotspots and ease final signoff. The second part of this blog discusses targeted PG stripes addition, another IR drop-centric technology to localize and remove the remaining hotspots.

In this blog, I will talk about the minimum period arc, which is a critical arc associated with the clock of a memory instance.

Power is HOT and it touches everything and everybody! But we can help with power analysis for your chip!! Do you want to: Sneak peek inside the schematic? Analyze power for various blocks? Identify the relation of hot cells with RTL? Explore annotation settings? Joules RTL Power Solution GUI (Graphical User Interface) helps you to analyze/debug the power estimation/results using several GUI capabilities...

Technology is changing the strategies we use to do things - oh so fast that 2010 seems like a distant past- within many spaces -- including the way we do our current topic of interest - Timing Signoff in Digital Implementation. The smaller nodes - le...

This blog introduces the Innovus Power Integrity Solution that integrates the Innovus Implementation System and Voltus IC Power Integrity Solution to alleviate signoff bottlenecks and provide faster convergence at the end of the flow.

If you are looking for a comprehensive training on block implementation with Innovus using the Stylus Common User Interface, look no further. This 3-day training, suitable for both beginner- and advanced designers, will take you through the complete digital block implementation flow, offering a detailed break-down of all implementation steps, while making you familiar with the graphical user interface, commands and attributes...

A library view contains electrical information that is used throughout design implementation starting from logic synthesis through design optimization to the final signoff verification.

This blog introduces the Tempus Power Integrity Solution that integrates the Tempus Timing Signoff Solution and Voltus IC Power Integrity Solution signoff engines to find silicon performance failures missed with traditional IR analysis.

Hi Everyone, Does the idea of using the best digital implementation tools on the market for your block sound interesting to you, but the full capacity is overkill, setup too daunting, or costs too high? If the answer is yes, do not worry; Cadence has...

With this blog starts a mini-series in Library Characterization Tidbits to share insights into the questions that our customers frequently ask. In this first edition, read about questions related to installation, configuration, and licensing of the Cadence Liberate Characterization solution.

This blog highlights the key capabilities and benefits of the Voltus ESD analysis flow.

Gone are the days when analyzing timing reports of the design used to take hours! We understand, your designs are complex and so is timing analysis. We cannot change the design, but we have made the timing analysis process easier for you during the synthesis stage. Are you ready to relax? Stop at channel-based Training Bytes on “Useful scripts for Timing Report Analysis” at https://support.cadence.com (Cadence login...

Thinking about how Liberate MX characterizes the constraint arcs, how the probe locations are picked up by the tool, what are the various controls associated with probing? Read the blog to find the answers.

This blog introduces the Voltus-Celsius Electro-Thermal Analysis RAK that will give you an accelerated start to achieve accurate co-analysis of a power-grid network on a chip-package-PCB system.

A recap of the blogs published in the Library Characterization Tidbits blog series.

With advanced-process nodes, the physical delay of a standard cell, net delay, and congestion all lead to a higher requirement on the netlist. Genus/Innovus iSpatial bridges synthesis and implementation with integrated core engines and unified physical optimization. This gives great power, performance, and area (PPA) results in complex SoC designs while maintaining quality and design schedule. Do you want to explore...

Are you concerned about the process to integrate third-party DFT insertion during synthesis? Stop worrying!! We have the solution! But: How it is done? What changes are recommended in the script while inserting third-party DFT in Genus? Are there different third-party DFT flows? To answer to all these questions is just a click away in the form of video on “Third-party DFT Insertion Flow in Genus Synthesis...

Voltus Voice is a blog series aimed at showcasing the diverse Voltus technologies to achieve high-performance, accuracy, and capacity for next-gen chip designs.

While using the Cadence Liberate Characterization solution or the Liberate Variety statistical characterization solution, have you encountered a situation where the search for constraints failed to return results within the specified range of arcs and then the related cell was marked as failed? If yes, then do read this blog.

We recently released the Innovus v20.1 software and you might be interested in learning about what's new or changed in the software. Here are some suggestions to get you up to speed: The best place to find all the details of the changes relative to v19.1, is to refer to the What's New document on the Cadence support site . If you want a quick intro to the 20.1 graphical user interface, view this demo that I created...

Read to know about the Liberate AMS command-line flow.