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LIBERATE 19.2 Base Release Now Available

By LIBERATE Team | 13 May 2019

The LIBERATE 19.2 production release is now available for download at Cadence Downloads . For information about supported platforms, compatibility with other Cadence tools, and details of key issues resolved in the LIBERATE 19.2 release, see the README.txt file. At the time of publishing, the link above was functional. If you encounter any links that are now obsolete, visit https://downloads.cadence.com , click...

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Liberate AMS | Bolt Job Distribution | Liberate Release Blog | Cadence blogs | characterization | liberate trio | LIBERATE19.2 | Liberate LV | Health Incident Report | Liberate Variety | Liberate MX | Digital Implementation | Ascava Distillation | Liberate | Characterization Portfolio | Liberty | Leakage Power Management
HLS Optimizations You Can't Do By Hand

By SeanDart | 10 May 2019

In my previous blog post , I talked about the Quality-of-Results (QoR) that are achievable using High-Level Synthesis tools like Stratus HLS and the fact that exploration of multiple RTLL architectures is often the feature that enables HLS users to beat hand-coded RTL flows in terms of QoR. That article raised the notion that "project schedule" is a critical factor when judging comparative QoR, and it often gets left...

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High-Level Synthesis | Stratus | SystemC | HLS
A new Electrostatic Discharge Analysis Solution – You Will Never Get Zapped!

By Priya E Joseph | 5 May 2019

“ It’s not what it is, it’s about what it can become ” -The Lorax by Dr. Seuss Have you recently reached out to open your car and received an unexpected shock…zap! There are no financial or health implications if the door handle of your car zaps you, but an Electrostatic Discharge (ESD) zap event can instantly destroy devices worth billions of dollars. Today, we are aware of the destructive nature of ESD in integrated...

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effective resistance | electromigration | clamps | electrostatic discharge | current density | differential voltage | EPS | Voltus | rule file | parallel processing | Innovus | EM | Charged Device Model | massively parallel | bump | ESD
2018 Annual HLS Survey Results

By dpursley | 13 Dec 2018

Earlier this year, we performed the annual high-level synthesis (HLS) industry survey to get an idea of the industry’s expectations of HLS. As in last year’s survey , approximately half of the responses were from current HLS users, and half were from non-users. This year’s anonymous survey focused on HLS usage and expectations. As usual, I’ll walk through the questions one by one below, but first let me give you what...

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High-Level Synthesis | 5G | survey | machine learning | Stratus | HLS
ECO with Stratus HLS and the Digital Implementation Flow

By dpursley | 12 Dec 2018

For years chip designers have dealt with ECO’s when their source code was written in RTL. But the move to high-level synthesis (HLS) means that their source code is now one step further removed from the gate level netlist. This naturally leaves a question, “What if I need an ECO on my Stratus project?” First and foremost, it’s important to understand that ECO’s are less common in the HLS flow. I’ll explain why in a...

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High-Level Synthesis | ECO | Conformal ECO Designer | Stratus | HLS
What's in it for Me in Innovus 18.10 Release?

By MJ Cad | 16 Oct 2018

At advanced nodes, there’s always a deep conflict between power, performance, and area (PPA) and design turnaround time (TAT). You already know Innovus Implementation System very smartly delivers PPA advantage and accelerates digital design TAT through various features, including its full-flow massively parallel architecture. Innovus 18.10 release takes all these benefits even further. In this blog, I will start with...

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Digital Implementation forums | Tempus | Release Page | Cadence Online Support | Digital Implementation | Innovus | full flow | blog
QoR with High-Level Synthesis. Can it really be better than hand-coded RTL?

By SeanDart | 2 Aug 2018

Whenever we talk to potential customers about Stratus HLS , we usually mention that many users get better quality of results (QoR) with a Stratus HLS flow than they did simply writing RTL by hand. Often, we are greeted with looks of skepticism or downright disbelief. We are usually asked the honest question: Can Stratus HLS really achieve better QoR than we can get using traditional RTL coding? I assure you that...

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High-Level Synthesis | Stratus | SystemC | HLS
A Decade of Building CODECs with High-Level Synthesis

By SeanDart | 9 Jul 2018

Over the past decade, we have seen a dramatic increase in the size of common video formats. Addressing this has required an evolution in the performance and complexity of video codecs, all the way from MPEG-2 to H.265. When designing hardware for these CODECs, high-level synthesis (HLS) has been a very common implementation tool of choice, due to the huge productivity gains provided by HLS and the ability of designers...

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High-Level Synthesis | Stratus | SystemC | HLS
High-Level Synthesis: The Secret Is Out

By dpursley | 12 Jun 2018

Gone is the day when companies (our customers) kept their use of high-level synthesis (HLS) quiet, a secret advantage over their competitors. As HLS usage became more widespread, the secret is out , and now the HLS community is talking and sharing experiences with each other. Take CDNLive , for instance. This year, HLS discussions are happening at the CDNLive shows worldwide. Since it’s extremely unlikely any of you...

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High-Level Synthesis | CDNLive | Stratus | HLS
Wind of Change in Hardware Design

By dpursley | 21 Feb 2018

After months of freezing temperatures in Pittsburgh, a 78 degree wind hit me as I stepped out of the office yesterday. While I’m sure it will be cold again by the time this blog gets published, yesterday made me think about how things are changing. In the 2017 annual HLS survey , we confirmed that wireless is the fastest growing market segment for high-level synthesis (HLS). That wasn’t much of a surprise, because...

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High-Level Synthesis | deep learning | machine learning | Stratus | HLS
Cadence Modus DFT at International Test Conference 2017

By Rob Knoth | 22 Nov 2017

While DAC is the focal point for the EDA industry, the test community travels in a slightly separate orbit. There are many conferences throughout the year, and around the globe, to help bridge the problems and solutions in academia and the industry....

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automotive | DFT | modus | ATPG | diagnostics | ITC
Functional Correctness—The Forgotten Benefit of HLS

By dpursley | 6 Nov 2017

I like to ask questions, because you learn a lot that way. In fact, I did a survey earlier this year and learned that high-level synthesis users’ experiences are exceeding the non-users’ expectations, and that HLS is being used for a wider variety of design types than even I knew. Recently I asked one of my favorite questions, and got an answer I truly didn’t expect. My favorite question to ask new HLS users: “What...

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High-Level Synthesis | Digital Implementation | HLS | verification
Faster and Smarter

By MeeraC | 5 Oct 2017

At the Cadence VIP dinner at Korea CDNLive last month, Paul Cunningham spoke about the state of the EDA industry, especially in the digital and signoff world. It all comes down to the productivity gap between the design diversity and complexity rising faster than the design schedules and other limited resources. This is our fundamental challenge. To overcome those challenges, designers must approach the challenge...

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cdnlive korea | deep learning | CDNLive | machine learning | digital | signoff
2017 Annual HLS Survey Results

By dpursley | 6 Jun 2017

As many of you know, Cadence (more correctly, “I”) recently performed an industry survey about HLS (High Level Synthesis) to get a fuller view of the productivity experiences and expectations from users and non-users alike. With nearly 200 responses, roughly half from HLS users and half not, we got a representative picture of what HLS users, potential users, and even skeptics believe about HLS. So let’s dive in. ...

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High-Level Synthesis | survey | Stratus | HLS
Designing for Low Power… Begin at the Beginning

By dpursley | 1 May 2017

So you have your RTL written, and it’s time to optimize to reduce power. If that’s your plan, you are likely leaving power on the table. It’s not that you can’t get a lot of savings with existing RTL synthesis tools (you certainly can!), but the biggest bang for the buck comes from early design decisions. Next time… start sooner! In fact, experts (not me, real experts ) estimate that optimal architectural (pre...

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Low Power | high level synthesis | power | HLS
“Great” Hardware Design in a Wireless World

By dpursley | 5 Apr 2017

As part three of the “ Making Hardware Design Great Again” series , let’s see how high-level synthesis (HLS) is helping designers create SoCs for WiFi, Bluetooth, and 5G. A common challenge in all three wireless spaces is that their standards are evolving… rapidly. Each new specification, or sub-specification, opens new opportunities. It’s a good opportunity for companies to establish themselves as providers for the...

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High-Level Synthesis | digital implementation | Digital Implementation | HLS
Making Hardware Design Great Again in 2017 - Part Deux

By dpursley | 28 Feb 2017

In part one of this series, we talked about the role of the hardware designer , specifically comparing the ideal version of the hardware designer with the real-world version. From the emails I received, this is a bittersweet reality for many readers of this blog. Today, we will revisit the life of a hardware designer whose company, like most of the leading semiconductor companies, is using a hardware design paradigm...

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High-Level Synthesis | digital implementation | Digital Implementation | HLS
Making Hardware Design Great Again in 2017

By dpursley | 22 Feb 2017

Ok, I admit it… that title is a blatant attempt to grab your attention. But it should also make you think. As a hardware designer, is your job great? Is it what you thought you’d be doing when you decided to become a designer? Is it, dare I say, fun? Or, like I hear so many times especially from those designing embedded integrated circuits , are you too bogged down in the muck of cranking out hardware implementations...

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High-Level Synthesis | digital implementation | Digital Implementation | HLS
Performance, Power, Area. It's All You Need to Know—or Is It?

By BrettCline | 21 Oct 2015

Whether it's in a technical paper, a pundit's article, or a live discussion with a customer, the term PPA—power, performance, and area—is always in the discussion. Of course, PPA is not simply one fixed point. Targets for PPA...

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High-Level Synthesis | PPA | Stratus | SystemC | HLS
Five-Minute Tutorial: Innovus Clock Tree Synthesis and Debugger

By Kari | 21 Aug 2015

Hi Everyone, Last time, our Five-Minute Tutorial focused on the new Innovus Placement Optimization . The next step in the flow would be inserting clock trees. Now that we can take advantage of the CCOpt engine to create clock trees, we can also concurrently optimize for timing. But you still have the choice of whether or not to do so. This is a decision that could be design-dependent, and you may want to try both...

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training | ccopt | clock tree synthesis | debugger | Digital Implementation | Innovus
Hot Summer for the High-Level Synthesis Community

By dpursley | 14 Jul 2015

Summer is usually a slow time of the year due to vacations, beautiful weather, and backyard barbeques. But for the HLS community, this summer has started off hot. At the 2015 Design Automation Conference, there was a lot going on with high-level syn...

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High-Level Synthesis | DAC 2015 | SystemC | Brian Bailey | HLS | SystemC Japan 2015
Five-Minute Tutorial: Innovus Placement Optimization

By Kari | 26 Jun 2015

Hi Everyone, Last time we got a quick look at The Innovus Standard Flow . Now I'd like to show you a bit more detail about some of the major steps. One of the new concepts in Innovus is how placement and pre-CTS timing optimization are now combined and interleaved. The GigaPlace placement engine is also new, and you will learn about its features. Click below to play the video (you'll need an active support.cadence...

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GigaPlace | Timing Optimization | Innovus | Placement
Five-Minute Tutorial: The Innovus Standard Flow

By Kari | 8 Jun 2015

Hi Everyone, Last week I highlighted a video featuring Innovus User Interface Tips . Now that you know how to get around, what next? Innovus has a new, more streamlined design flow. Most designs should start with what's called the Standard Flow. There is a great document on support.cadence.com outlining this flow. I found it very interesting, and I can't wait to try it on my next design. You'll need an active support...

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design flow | Digital Implementation | Innovus | five minute tutorial
Five-Minute Tutorial: Innovus User Interface Tips

By Kari | 2 Jun 2015

Hi Everyone, No doubt by now you have heard about the Innovus Implementation System , our next-generation physical implementation solution. It's always a bit scary to move to a new tool, but let me assure you that if you are a current Encounter user, you will be able to get around just fine in the Innovus system. A lot of the user interface will look very familiar to you, but there are some important changes and improvements...

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UI | Digital Implementation | Innovus | five minute tutorial
Five Things You Didn’t Know About High-level Synthesis

By dpursley | 24 Apr 2015

Most of you have heard about the promises of high-level synthesis (HLS). Things like improved productivity, quality of results (QoR), and verification all dominate the high-level synthesis collateral, including ours. So here, I’ll mention five ...

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High-Level Synthesis | ECO | Conformal ECO Designer | cadence | Blu Wireless | Forte | Stratus | HLS

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