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Are You Stuck While Synthesizing Your Design Due to Low-Power Issues? We Have the Solution!

By Neha Joshi | 31 Mar 2020

Optimizing power can be a very convoluted and crucial process. To make design chips meet throughput goals along with optimal power consumption, you need to plan right from the beginning!

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Low Power | Logic Design
Library Characterization Tidbits: Validating Libraries Effectively

By Jommy | 23 Mar 2020

In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for Liberate LV Library Validation.

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Liberate LV | timing validation | Digital Implementation | interpolation error | library validation | RAKs
Library Characterization Tidbits: Exploring Intuitive Means to Characterize Large Mixed-Signal Blocks

By AbhaRawat | 6 Mar 2020

Let’s review a key characteristic feature of Cadence Liberate AMS Mixed-Signal Characterization that offers to you ease of use along with many other benefits like automation of standard Liberty model creation and improvement of up to 20X throughput.

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Liberate AMS | video | library generation | pin capacitance | Mixed-Signal | library characterization | shell libraries | Liberate Characterization Portfolio | Liberty | Virtuoso ADE Explorer | Virtuoso ADE Assembler
Library Characterization Tidbits: Over the Clouds and Beyond with Arm-Based Graviton and Cadence Liberate Trio

By Seena Shankar | 21 Feb 2020

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors.

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Liberate Trio Characterization | Unified Flow | Variation Modeling | artificial intelligence | ARM-based Graviton Processors | liberate blog | Amazon Web Services | Multi-PVT | Liberate LV | Liberate Variety | machine learning | aws | PVT corners | Liberate | Liberate Characterization Portfolio | TSMC OPI Ecosystem Forum 2019
Library Characterization Tidbits: Liberate MX for Memory Characterization Video Series

By Jommy | 10 Feb 2020

As we embark upon our blogging journey again in 2020, in this Library Characterization Tidbits series, we want to draw your attention to an informative video series on memory characterization, which is available on the Cadence support portal.

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Liberate MX validation flow | memory characterization | liberate_mx custom flow | standard custom flow | full custom flow | liberate_mx standard custom flow | compiler characterization | liberate_mx full custom flow | liberate_mx | Liberate MX | Characterization Portfolio
Library Characterization Tidbits: A Matrix for Your Reference

By Jommy | 19 Dec 2019

When working on multiple tools of the Cadence Liberate Characterization Portfolio, do you tend to get confused about which commands or parameters are supported in a specific tool? Read more...

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parameter | Liberate AMS | Matrix | liberate blog | Liberate LV | Commands | Liberate Variety | Liberate MX | Liberate | Liberate Characterization Portfolio
2019 Annual HLS Survey Results

By dpursley | 18 Dec 2019

Each year, we survey the industry to get an idea of the industry’s experiences and expectations of high-level synthesis (HLS). As in last year’s survey , approximately half of the responses were from current HLS users, and half were from non-users. This year’s anonymous survey focused on productivity. Spoiler alert : Users find the HLS flow to be over 2.5x more productive for design and nearly 4x more productive...

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Library Characterization Tidbits: Creating Statistical Libraries for Standard Cells and IO Cells

By Aravind R | 5 Dec 2019

Let’s read how you can use the Liberate Variety statistical characterization solution of the Cadence Liberate Characterization Portfolio for generating the statistical characterization models for standard cell libraries.

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local variation | statistical characterization | AOCV | characterization | liberate trio | mismatch analysis | Liberate Variety | Monte Carlo | standard cells | global variation | lvf | Liberate | Liberate Characterization Portfolio
Library Characterization Tidbits: Basics of Standard Cell Characterization and More

By AbhaRawat | 20 Nov 2019

Characterization of standard cell libraries using the Liberate Characterization solution is broadly divided into five stages. Read this blog to know about the related basics and the step-by-step procedure.

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tidbits | SPICE netlist | Standard Cell | characterization | Liberty Files | Spectre | Library Characterization Tidbit | Digital Implementation | Characterization Solution | Liberate | Inside-View | Liberate Characterization Portfolio | Rapid Adoption Kits | ECSM | RAKs | CCS | Model Files
Library Characterization Tidbits: Reasons to Start Following This New Blog Series

By AbhaRawat | 7 Nov 2019

Library Characterization Tidbits is a blog series aimed at providing insight into the useful software and documentation enhancements in the LIBERATE release.

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Liberate AMS | videos | Liberate LV | Liberate Variety | library characterization | Application Notes | Liberate MX | training bytes | Liberate | Liberate Characterization Portfolio | RAKs
Upcoming Webinar: AI Accelerator Design with Stratus HLS

By dpursley | 17 Sep 2019

There is no doubt that 2019 has seen an explosion of artificial intelligence/machine learning usage for Stratus HLS. In fact, this momentum started in 2017. Noting the increase in machine learning applications in our user base, we researched how to efficiently move from a TensorFlow model to hardware via Stratus HLS . By July 2018, AI startup Syntiant was talking at DAC about how they went from spec to tapeout in six...

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High-Level Synthesis | webinars | TensorFlow | machine learning | Stratus | SystemC | HLS
Now Access Online Support Directly from the Tool Interface

By MJ Cad | 28 Aug 2019

As designs become complex and performance targets increase, time shrinks. Designers need to minimize time setting up design flows or trying to find workaround for many issues that might occur during tape out. The Cadence Online Support portal ensures 24x7 technical assistance to quickly address your technical issues and queries. In our continuous effort to improve the usability of the Online Support portal and efficiency...

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Digital Implementation forums | Cadence Online Support | Digital Implementation | Innovus
Exploring AI / Machine Learning Implementations with Stratus HLS

By SeanDart | 19 Jun 2019

A lot of AI design is done in software and, while much of it will remain there, increasing numbers of designs are finding their way into hardware. There are multiple reasons for this including the important goals of achieving lower power or higher performance for critical parts of the AI process. Imagine you need dramatically improved rate of object recognition in automated-driving applications. Implementing an AI...

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High-Level Synthesis | TensorFlow | machine learning | Stratus | SystemC | HLS | AI
Need Help with Liberate Commands and Parameters?

By Jommy | 3 Jun 2019

Alexa, what is square root of 12547858? Within some nanoseconds, Alexa gives you the answer to it. That's how convenient technology has made things for us! How cool would it be if Alexa could get some help with the usage of parameters or commands while scripting? Well, we don't have Alexa to your rescue yet, but do have a cool help functionality that could save you time and effort of pulling out a reference manual...

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parameter | Liberate AMS | liberate blog | liberate trio | Liberate LV | Commands | Liberate Variety | Liberate MX | Cadence Help | Digital Implementation | Liberate | Liberty
LIBERATE 19.2 Base Release Now Available

By LIBERATE Team | 13 May 2019

The LIBERATE 19.2 production release is now available for download at Cadence Downloads . For information about supported platforms, compatibility with other Cadence tools, and details of key issues resolved in the LIBERATE 19.2 release, see the README.txt file. At the time of publishing, the link above was functional. If you encounter any links that are now obsolete, visit https://downloads.cadence.com , click...

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Liberate AMS | Bolt Job Distribution | Liberate Release Blog | Cadence blogs | characterization | liberate trio | LIBERATE19.2 | Liberate LV | Health Incident Report | Liberate Variety | Liberate MX | Digital Implementation | Ascava Distillation | Liberate | Characterization Portfolio | Liberty | Leakage Power Management
HLS Optimizations You Can't Do By Hand

By SeanDart | 10 May 2019

In my previous blog post , I talked about the Quality-of-Results (QoR) that are achievable using High-Level Synthesis tools like Stratus HLS and the fact that exploration of multiple RTLL architectures is often the feature that enables HLS users to beat hand-coded RTL flows in terms of QoR. That article raised the notion that "project schedule" is a critical factor when judging comparative QoR, and it often gets left...

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High-Level Synthesis | Stratus | SystemC | HLS
A new Electrostatic Discharge Analysis Solution – You Will Never Get Zapped!

By Priya E Joseph | 5 May 2019

“ It’s not what it is, it’s about what it can become ” -The Lorax by Dr. Seuss Have you recently reached out to open your car and received an unexpected shock…zap! There are no financial or health implications if the door handle of your car zaps you, but an Electrostatic Discharge (ESD) zap event can instantly destroy devices worth billions of dollars. Today, we are aware of the destructive nature of ESD in integrated...

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effective resistance | electromigration | clamps | electrostatic discharge | current density | differential voltage | EPS | Voltus | rule file | parallel processing | Innovus | EM | Charged Device Model | massively parallel | bump | ESD
2018 Annual HLS Survey Results

By dpursley | 13 Dec 2018

Earlier this year, we performed the annual high-level synthesis (HLS) industry survey to get an idea of the industry’s expectations of HLS. As in last year’s survey , approximately half of the responses were from current HLS users, and half were from non-users. This year’s anonymous survey focused on HLS usage and expectations. As usual, I’ll walk through the questions one by one below, but first let me give you what...

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High-Level Synthesis | 5G | survey | machine learning | Stratus | HLS
ECO with Stratus HLS and the Digital Implementation Flow

By dpursley | 12 Dec 2018

For years chip designers have dealt with ECO’s when their source code was written in RTL. But the move to high-level synthesis (HLS) means that their source code is now one step further removed from the gate level netlist. This naturally leaves a question, “What if I need an ECO on my Stratus project?” First and foremost, it’s important to understand that ECO’s are less common in the HLS flow. I’ll explain why in a...

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High-Level Synthesis | ECO | Conformal ECO Designer | Stratus | HLS
What's in it for Me in Innovus 18.10 Release?

By MJ Cad | 16 Oct 2018

At advanced nodes, there’s always a deep conflict between power, performance, and area (PPA) and design turnaround time (TAT). You already know Innovus Implementation System very smartly delivers PPA advantage and accelerates digital design TAT through various features, including its full-flow massively parallel architecture. Innovus 18.10 release takes all these benefits even further. In this blog, I will start with...

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Digital Implementation forums | Tempus | Release Page | Cadence Online Support | Digital Implementation | Innovus | full flow | blog
QoR with High-Level Synthesis. Can it really be better than hand-coded RTL?

By SeanDart | 2 Aug 2018

Whenever we talk to potential customers about Stratus HLS , we usually mention that many users get better quality of results (QoR) with a Stratus HLS flow than they did simply writing RTL by hand. Often, we are greeted with looks of skepticism or downright disbelief. We are usually asked the honest question: Can Stratus HLS really achieve better QoR than we can get using traditional RTL coding? I assure you that...

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High-Level Synthesis | Stratus | SystemC | HLS
A Decade of Building CODECs with High-Level Synthesis

By SeanDart | 9 Jul 2018

Over the past decade, we have seen a dramatic increase in the size of common video formats. Addressing this has required an evolution in the performance and complexity of video codecs, all the way from MPEG-2 to H.265. When designing hardware for these CODECs, high-level synthesis (HLS) has been a very common implementation tool of choice, due to the huge productivity gains provided by HLS and the ability of designers...

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High-Level Synthesis | Stratus | SystemC | HLS
High-Level Synthesis: The Secret Is Out

By dpursley | 12 Jun 2018

Gone is the day when companies (our customers) kept their use of high-level synthesis (HLS) quiet, a secret advantage over their competitors. As HLS usage became more widespread, the secret is out , and now the HLS community is talking and sharing experiences with each other. Take CDNLive , for instance. This year, HLS discussions are happening at the CDNLive shows worldwide. Since it’s extremely unlikely any of you...

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High-Level Synthesis | CDNLive | Stratus | HLS
Wind of Change in Hardware Design

By dpursley | 21 Feb 2018

After months of freezing temperatures in Pittsburgh, a 78 degree wind hit me as I stepped out of the office yesterday. While I’m sure it will be cold again by the time this blog gets published, yesterday made me think about how things are changing. In the 2017 annual HLS survey , we confirmed that wireless is the fastest growing market segment for high-level synthesis (HLS). That wasn’t much of a surprise, because...

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High-Level Synthesis | deep learning | machine learning | Stratus | HLS
Cadence Modus DFT at International Test Conference 2017

By Rob Knoth | 22 Nov 2017

While DAC is the focal point for the EDA industry, the test community travels in a slightly separate orbit. There are many conferences throughout the year, and around the globe, to help bridge the problems and solutions in academia and the industry....

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Tags:

automotive | DFT | modus | ATPG | diagnostics | ITC

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