Digital Implementation Blogs

Low-Power synthesis is one of the important stages in the full IC flow. Here, you synthesize the design from behavioral description to gates while optimizing for dynamic and leakage power using various techniques. We understand that it is not always easy to estimate power, but Cadence offers a solution in the form of a low-power synthesis flow with Genus. Are you interested in exploring: What the complete low-power...

A Logic Synthesis is a process of optimizing the design's area, timing, and power. You might be a beginner in the synthesis world, but we can help you sail through it smoothly. It's time to introduce yourself to our tool for synthesis , Genus Synthesis Solution. The ultimate goal of the Cadence ® Genus Synthesis Solution is very simple: deliver the best possible productivity during register-transfer-level (RTL) design...

No matter how your name is spelt in different countries, and how they say it, once they get to know you, people identify you as the same person. Ah! this is Chris, Cris, Kris, Kirshner, or Krishna. And I know this dude, even though he has transformed since I last saw him, and is 10 years older than what I remember. Likewise, different tools have different ways of naming the same design object and the default rules...

What comes to your mind when we say Genus Layout GUI (Graphical User Interface)? You picture the floorplan filled with instances and objects. Imagine you need to highlight the specific instance or timing path in GUI? Do you think it’s tricky? Not at all!! Genus Synthesis Solution GUI (Graphical User Interface) helps you view and highlight the instances and timing results to better explore/debug your design. Now...

In the first post of our " Simplifying Power Signoff for HPC Systems" blog series, we discuss how the Voltus event-based power analysis flow helps in making accurate power estimation for large scale and high-performance designs early in the development process.

This post describes a channel of videos created to show how to floorplan a design using Innovus Implementation System software.

With the shrinking gemoetries and data-intensive endeavours of the upcoming industries like IoT, Robotics, Self-Driving Cars, 5G and 6G phones, designs are getting more complex. There are many challenges like congestion, routing, on-chip variations, and unconstrained paths that must be addressed. Cadence 24X7 support and rapid adoption kits (RAKs) helps customers by providing ready support and quick resolution.

Learn how to navigate through the challenges of power and thermal integrity analysis in 3D-ICs with the CadenceTECHTALK webinar on 23rd March, 2022.

In the final part of our "Hierarchical Power Integrity Analysis" blog series, we explore how to use the reduced xPGV models at the top level to improve chip design productivity.

Gone are the days when process shrinking was considered as the primary driver of product innovation and improved system performance. The path most are taking leads to the world of “More than Moore.” Vertical Stacking of heterogeneous chips and chiplets is the name of the game . It will have a significant impact on applications that require ultra-high-performance and low power, such as multi-core CPUs, GPUs, packet...

Scan compression is critical for addressing the rapid rise of test costs without sacrificing coverage requirements. Although it has been widely adopted, it has its limitations. In today's era demand is not just high coverage but also the ability to verify that the design is working in the field. A unified compression is an approach that unifies scan compression and logic built-in self-test (LBIST). It leverages physically...

A recap of the power integrity posts in the Voltus Voice blog series through 2021.

This blog discusses the implementation of task assistant for the Voltus ESD analysis flow. ESD task assistant is an in-tool help access medium that facilitates the quick resolution of your ESD questions.

In part 2 of our "Hierarchical Power Integrity Analysis" blog series, we discuss how to implement the hierarchical power integrity solution to create xPGV models of the IP blocks.

Cadence Stylus UI streamlines the RTL-to-Signoff design flow, bringing all the Cadence digital synthesis and implementation tools together with ease. This blog shares tips to seamlessly migrate your Voltus legacy flows to Stylus UI.

When you achieve the credit for proficiency, do you want to show it to the world? We know it isn’t easy to carry the actual physical badge (certificate) everywhere today. Why? Expenses, pandemic, making a list where to travel, to whom to show etc. Don’t worry! We have an easy and cost-free solution for this. Become Cadence Certified with Digital Badges. How? We have introduced courses for Digital Badge Exams for...

To help you tackle contemporary challenges related to extremely large design power signoff, the Voltus XM technology provides fast, accurate, and memory efficient analysis. Click here to know more.

A glitch, although, is an unnecessary signal transition in your design. But its impact can be tremendous. And yes, glitch contributes to glitch power as well. It can affect the power dissipation by many folds as it could be a significant part of your dynamic power consumption. So even though it is unnecessary but you must identify the glitch power!! How to analyze glitch power? Relax!! And leave glitch for Joules...

Learn to verify low-power designs using Conformal ® Low-Power Verification. We've added a few super short videos in this channel to help you get going: Conformal Verify CPF Flow Graphical Interface Introduction Conformal Low Power Verify CPF Rule Filtering Here is the course to take you a little more in-depth into the concepts and techniques used for such verification: Conformal Low Power Verification ...

Do you want to determine the weak spots in your power grid network at the start of physical design? Then go ahead and read this blog to learn more about the different resistance analysis techniques to prevent a voltage drop and model a robust power grid.

Hello Digital Designers, Innovus 21.1 released a few weeks ago and you might be curious about what’s new and improved in the tool. Here are three quick ways to get up to speed: Watch the short demo of the Innovus 21.1 GUI that I captured to provide an overview of the user interface. If you already use Innovus, I would recommend my go-to source, created by our Pubs team, What’s New in Innovus Stylus Common UI...

In this blog, Rajat Chaudhry (Product Management Director of Voltus) tells us how Voltus has introduced several innovative technologies to address power signoff challenges, while integrating seamlessly with Cadence IC, package, PCB, and system tools.

Design for Test (DFT) techniques provide measures to test the manufactured device for quality and coverage comprehensively. You might encounter Error or Warning messages while inserting scan during the synthesis stage. We know it is a little tricky to resolve DFT Errors and Warning. But don't worry!! We can help provide guidance. For example, the Error or Warning could be related to checking DFT rules, reporting, defining...

In the concluding blog of our "Demystifying ESD" series, we walk you through the features of the Voltus Electrostatic Discharge (ESD) analysis reports that provide a clear insight on your design's vulnerability to ESD, from the early-design phase to tapeout.

Design for Test (DFT) techniques provide measures to comprehensively test the manufactured device for quality and coverage. During the synthesis stage, you might encounter DFT violations that need to be resolved. We know it is a complicated process to debug the DFT violations. But don’t worry!! We can help you to sail through this. Check the DFT Analyzer capability, which helps in graphical debugging of DFT violations...