Cadence Community

Library Characterization Tidbits: Reuse to Recharacterize - Improve Productivity with Liberate MX

By KamleshSinghDodiya | 15 May 2020

A write up on how Liberate MX effectively enables you to characterize only the failed or new arcs.

0 Comments

Tags:

memory characterization | incremental run | timing validation | Liberate MX | Digital Implementation | interpolation error | library validation | Rapid Adoption Kits | RAKs
Library Characterization Tidbits: Recharacterize What Matters - Save Time!

By AbhaRawat | 30 Apr 2020

Read how the Cadence Liberate Characterization solution effectively enables you to characterize only the failed or new arcs of a standard cell.

0 Comments

Tags:

tidbits | Standard Cell | library characterization | Application Notes | missing arcs | Library Characterization Tidbit | Digital Implementation | ldb | failed arcs | Characterization Solution | Liberate | Liberate Characterization Portfolio
Library Characterization Tidbits: Rewind and Replay

By Jommy | 16 Apr 2020

A recap of the blogs published in the Library Characterization Tidbits blog series.

0 Comments

Tags:

Liberate AMS | Liberate LV | RAK | Liberate Variety | library characterization | Application Notes | Liberate MX | training bytes | Library Characterization Tidbit | Liberate Characterization Portfolio
Joules – Power Exploration Capabilities

By Neha Joshi | 10 Apr 2020

Several tools can generate power reports based on libraries & stimulus. The issue is what's NEXT? Is there any scope to improve power consumption of my design? What is the best-case power? Pin-point hot spots in my design? How to recover wasted power? And here is the solution in form of Joules RTL Power Exploration . Joules’ framework for power exploration and power implementation/recovery is stimulus based...

0 Comments

Tags:

Low Power | Joules | Logic Design | Power Analysis
Exploring Genus-Joules Integration is just a click away!!

By Neha Joshi | 10 Apr 2020

Joules RTL Power Solution provides a cockpit for RTL designers to explore and optimize the power efficiency of their designs. But this capability is now not just limited to RTL designers!! Yes, you as a synthesis designer too can use the power analysis capabilities of Joules from within Genus Synthesis Solution!! But: How to do it? Is there any specific switch required? What is the flow/script when Joules is...

0 Comments

Tags:

Low Power | Genus | Joules | Logic Design | Power Analysis
Genus Synthesis Solution – Introduction to Stylus Common UI

By Neha Joshi | 9 Apr 2020

The Cadence® Genus Synthesis Solution, Innovus Implementation System, and Tempus Timing Signoff Solution have a lot of shared functionality, but in the past, the separate legacy user interfaces (UIs) created a lot of differences. A new common user interface that the Genus solution shares with the Innovus and Tempus solutions streamlines flow development and simplifies usability across the complete Cadence digital flow...

0 Comments

Tags:

Genus | Logic Design | common | stylus
Innovus Implementation System: What Is Stylus UI?

By VNelson | 6 Apr 2020

Hi Everyone, Many of you would have heard about the Cadence Stylus Common UI and are wondering what it is and what the advantages might be to use it versus legacy UI. The webinar answers the following questions: Why did Cadence develop Stylus UI and what is Stylus Common UI? How does someone invoke and use the Stylus Common UI? What are some of the important and useful features of the Stylus Common UI? ...

0 Comments
Are You Stuck While Synthesizing Your Design Due to Low-Power Issues? We Have the Solution!

By Neha Joshi | 31 Mar 2020

Optimizing power can be a very convoluted and crucial process. To make design chips meet throughput goals along with optimal power consumption, you need to plan right from the beginning!

0 Comments

Tags:

Low Power | Logic Design
Library Characterization Tidbits: Validating Libraries Effectively

By Jommy | 23 Mar 2020

In this blog, I will brief you about two very useful Rapid Adoption Kits (RAKs) for Liberate LV Library Validation.

0 Comments

Tags:

Liberate LV | timing validation | Digital Implementation | interpolation error | library validation | RAKs
Library Characterization Tidbits: Exploring Intuitive Means to Characterize Large Mixed-Signal Blocks

By AbhaRawat | 6 Mar 2020

Let’s review a key characteristic feature of Cadence Liberate AMS Mixed-Signal Characterization that offers to you ease of use along with many other benefits like automation of standard Liberty model creation and improvement of up to 20X throughput.

0 Comments

Tags:

Liberate AMS | video | library generation | pin capacitance | Mixed-Signal | library characterization | shell libraries | Liberate Characterization Portfolio | Liberty | Virtuoso ADE Explorer | Virtuoso ADE Assembler
Library Characterization Tidbits: Over the Clouds and Beyond with Arm-Based Graviton and Cadence Liberate Trio

By Seena Shankar | 21 Feb 2020

Cadence Liberate Trio Characterization Suite, ARM-based Graviton Processors, and Amazon Web Services (AWS) Cloud have joined forces to cater to the High-Performance Computing, Machine Learning/Artificial Intelligence, and Big Data Analytics sectors.

0 Comments

Tags:

Liberate Trio Characterization | Unified Flow | Variation Modeling | artificial intelligence | ARM-based Graviton Processors | liberate blog | Amazon Web Services | Multi-PVT | Liberate LV | Liberate Variety | machine learning | aws | PVT corners | Liberate | Liberate Characterization Portfolio | TSMC OPI Ecosystem Forum 2019
Library Characterization Tidbits: Liberate MX for Memory Characterization Video Series

By Jommy | 10 Feb 2020

As we embark upon our blogging journey again in 2020, in this Library Characterization Tidbits series, we want to draw your attention to an informative video series on memory characterization, which is available on the Cadence support portal.

0 Comments

Tags:

Liberate MX validation flow | memory characterization | liberate_mx custom flow | standard custom flow | full custom flow | liberate_mx standard custom flow | compiler characterization | liberate_mx full custom flow | liberate_mx | Liberate MX | Characterization Portfolio
Library Characterization Tidbits: A Matrix for Your Reference

By Jommy | 19 Dec 2019

When working on multiple tools of the Cadence Liberate Characterization Portfolio, do you tend to get confused about which commands or parameters are supported in a specific tool? Read more...

0 Comments

Tags:

parameter | Liberate AMS | Matrix | liberate blog | Liberate LV | Commands | Liberate Variety | Liberate MX | Liberate | Liberate Characterization Portfolio
2019 Annual HLS Survey Results

By dpursley | 18 Dec 2019

Each year, we survey the industry to get an idea of the industry’s experiences and expectations of high-level synthesis (HLS). As in last year’s survey , approximately half of the responses were from current HLS users, and half were from non-users. This year’s anonymous survey focused on productivity. Spoiler alert : Users find the HLS flow to be over 2.5x more productive for design and nearly 4x more productive...

0 Comments
Library Characterization Tidbits: Creating Statistical Libraries for Standard Cells and IO Cells

By Aravind R | 5 Dec 2019

Let’s read how you can use the Liberate Variety statistical characterization solution of the Cadence Liberate Characterization Portfolio for generating the statistical characterization models for standard cell libraries.

0 Comments

Tags:

local variation | statistical characterization | AOCV | characterization | liberate trio | mismatch analysis | Liberate Variety | Monte Carlo | standard cells | global variation | lvf | Liberate | Liberate Characterization Portfolio
Library Characterization Tidbits: Basics of Standard Cell Characterization and More

By AbhaRawat | 20 Nov 2019

Characterization of standard cell libraries using the Liberate Characterization solution is broadly divided into five stages. Read this blog to know about the related basics and the step-by-step procedure.

0 Comments

Tags:

tidbits | SPICE netlist | Standard Cell | characterization | Liberty Files | Spectre | Library Characterization Tidbit | Digital Implementation | Characterization Solution | Liberate | Inside-View | Liberate Characterization Portfolio | Rapid Adoption Kits | ECSM | RAKs | CCS | Model Files
Library Characterization Tidbits: Reasons to Start Following This New Blog Series

By AbhaRawat | 7 Nov 2019

Library Characterization Tidbits is a blog series aimed at providing insight into the useful software and documentation enhancements in the LIBERATE release.

0 Comments

Tags:

Liberate AMS | videos | Liberate LV | Liberate Variety | library characterization | Application Notes | Liberate MX | training bytes | Liberate | Liberate Characterization Portfolio | RAKs
Upcoming Webinar: AI Accelerator Design with Stratus HLS

By dpursley | 17 Sep 2019

There is no doubt that 2019 has seen an explosion of artificial intelligence/machine learning usage for Stratus HLS. In fact, this momentum started in 2017. Noting the increase in machine learning applications in our user base, we researched how to efficiently move from a TensorFlow model to hardware via Stratus HLS . By July 2018, AI startup Syntiant was talking at DAC about how they went from spec to tapeout in six...

0 Comments

Tags:

High-Level Synthesis | webinars | TensorFlow | machine learning | Stratus | SystemC | HLS
Now Access Online Support Directly from the Tool Interface

By MJ Cad | 28 Aug 2019

As designs become complex and performance targets increase, time shrinks. Designers need to minimize time setting up design flows or trying to find workaround for many issues that might occur during tape out. The Cadence Online Support portal ensures 24x7 technical assistance to quickly address your technical issues and queries. In our continuous effort to improve the usability of the Online Support portal and efficiency...

0 Comments

Tags:

Digital Implementation forums | Cadence Online Support | Digital Implementation | Innovus
Exploring AI / Machine Learning Implementations with Stratus HLS

By SeanDart | 19 Jun 2019

A lot of AI design is done in software and, while much of it will remain there, increasing numbers of designs are finding their way into hardware. There are multiple reasons for this including the important goals of achieving lower power or higher performance for critical parts of the AI process. Imagine you need dramatically improved rate of object recognition in automated-driving applications. Implementing an AI...

0 Comments

Tags:

High-Level Synthesis | TensorFlow | machine learning | Stratus | SystemC | HLS | AI
Need Help with Liberate Commands and Parameters?

By Jommy | 3 Jun 2019

Alexa, what is square root of 12547858? Within some nanoseconds, Alexa gives you the answer to it. That's how convenient technology has made things for us! How cool would it be if Alexa could get some help with the usage of parameters or commands while scripting? Well, we don't have Alexa to your rescue yet, but do have a cool help functionality that could save you time and effort of pulling out a reference manual...

0 Comments

Tags:

parameter | Liberate AMS | liberate blog | liberate trio | Liberate LV | Commands | Liberate Variety | Liberate MX | Cadence Help | Digital Implementation | Liberate | Liberty
LIBERATE 19.2 Base Release Now Available

By LIBERATE Team | 13 May 2019

The LIBERATE 19.2 production release is now available for download at Cadence Downloads . For information about supported platforms, compatibility with other Cadence tools, and details of key issues resolved in the LIBERATE 19.2 release, see the README.txt file. At the time of publishing, the link above was functional. If you encounter any links that are now obsolete, visit https://downloads.cadence.com , click...

0 Comments

Tags:

Liberate AMS | Bolt Job Distribution | Liberate Release Blog | Cadence blogs | characterization | liberate trio | LIBERATE19.2 | Liberate LV | Health Incident Report | Liberate Variety | Liberate MX | Digital Implementation | Ascava Distillation | Liberate | Characterization Portfolio | Liberty | Leakage Power Management
HLS Optimizations You Can't Do By Hand

By SeanDart | 10 May 2019

In my previous blog post , I talked about the Quality-of-Results (QoR) that are achievable using High-Level Synthesis tools like Stratus HLS and the fact that exploration of multiple RTLL architectures is often the feature that enables HLS users to beat hand-coded RTL flows in terms of QoR. That article raised the notion that "project schedule" is a critical factor when judging comparative QoR, and it often gets left...

0 Comments

Tags:

High-Level Synthesis | Stratus | SystemC | HLS
A new Electrostatic Discharge Analysis Solution – You Will Never Get Zapped!

By Priya E Joseph | 5 May 2019

“ It’s not what it is, it’s about what it can become ” -The Lorax by Dr. Seuss Have you recently reached out to open your car and received an unexpected shock…zap! There are no financial or health implications if the door handle of your car zaps you, but an Electrostatic Discharge (ESD) zap event can instantly destroy devices worth billions of dollars. Today, we are aware of the destructive nature of ESD in integrated...

0 Comments

Tags:

effective resistance | electromigration | clamps | electrostatic discharge | current density | differential voltage | EPS | Voltus | rule file | parallel processing | Innovus | EM | Charged Device Model | massively parallel | bump | ESD
2018 Annual HLS Survey Results

By dpursley | 13 Dec 2018

Earlier this year, we performed the annual high-level synthesis (HLS) industry survey to get an idea of the industry’s expectations of HLS. As in last year’s survey , approximately half of the responses were from current HLS users, and half were from non-users. This year’s anonymous survey focused on HLS usage and expectations. As usual, I’ll walk through the questions one by one below, but first let me give you what...

0 Comments

Tags:

High-Level Synthesis | 5G | survey | machine learning | Stratus | HLS

Digital Implementation Blogs