Digital Implementation Blogs

In part 2 of our "Hierarchical Power Integrity Analysis" blog series, we discuss how to implement the hierarchical power integrity solution to create xPGV models of the IP blocks.

Cadence Stylus UI streamlines the RTL-to-Signoff design flow, bringing all the Cadence digital synthesis and implementation tools together with ease. This blog shares tips to seamlessly migrate your Voltus legacy flows to Stylus UI.

When you achieve the credit for proficiency, do you want to show it to the world? We know it isn’t easy to carry the actual physical badge (certificate) everywhere today. Why? Expenses, pandemic, making a list where to travel, to whom to show etc. Don’t worry! We have an easy and cost-free solution for this. Become Cadence Certified with Digital Badges. How? We have introduced courses for Digital Badge Exams for...

To help you tackle contemporary challenges related to extremely large design power signoff, the Voltus XM technology provides fast, accurate, and memory efficient analysis. Click here to know more.

A glitch, although, is an unnecessary signal transition in your design. But its impact can be tremendous. And yes, glitch contributes to glitch power as well. It can affect the power dissipation by many folds as it could be a significant part of your dynamic power consumption. So even though it is unnecessary but you must identify the glitch power!! How to analyze glitch power? Relax!! And leave glitch for Joules...

Learn to verify low-power designs using Conformal ® Low-Power Verification. We've added a few super short videos in this channel to help you get going: Conformal Verify CPF Flow Graphical Interface Introduction Conformal Low Power Verify CPF Rule Filtering Here is the course to take you a little more in-depth into the concepts and techniques used for such verification: Conformal Low Power Verification ...

Do you want to determine the weak spots in your power grid network at the start of physical design? Then go ahead and read this blog to learn more about the different resistance analysis techniques to prevent a voltage drop and model a robust power grid.

Hello Digital Designers, Innovus 21.1 released a few weeks ago and you might be curious about what’s new and improved in the tool. Here are three quick ways to get up to speed: Watch the short demo of the Innovus 21.1 GUI that I captured to provide an overview of the user interface. If you already use Innovus, I would recommend my go-to source, created by our Pubs team, What’s New in Innovus Stylus Common UI...

In this blog, Rajat Chaudhry (Product Management Director of Voltus) tells us how Voltus has introduced several innovative technologies to address power signoff challenges, while integrating seamlessly with Cadence IC, package, PCB, and system tools.

Design for Test (DFT) techniques provide measures to test the manufactured device for quality and coverage comprehensively. You might encounter Error or Warning messages while inserting scan during the synthesis stage. We know it is a little tricky to resolve DFT Errors and Warning. But don't worry!! We can help provide guidance. For example, the Error or Warning could be related to checking DFT rules, reporting, defining...

In the concluding blog of our "Demystifying ESD" series, we walk you through the features of the Voltus Electrostatic Discharge (ESD) analysis reports that provide a clear insight on your design's vulnerability to ESD, from the early-design phase to tapeout.

Design for Test (DFT) techniques provide measures to comprehensively test the manufactured device for quality and coverage. During the synthesis stage, you might encounter DFT violations that need to be resolved. We know it is a complicated process to debug the DFT violations. But don’t worry!! We can help you to sail through this. Check the DFT Analyzer capability, which helps in graphical debugging of DFT violations...

Timing closure is one of the most crucial steps of a digital design. Therefore, to meet timing at the later stages of design signoff, it is imperative to consider timing analysis within the synthesis stage. We know real designs are complex, and so is the timing analysis. Unfortunately, we cannot reduce the complexity, but we can make the ride smooth during the timing analysis journey!! The trick is to use a GUI-based...

Hello Digital Designers, Interested in learning more about how to implement a low-power design? Do you have multiple voltage islands that need level-shifting, and isolation, and also require a CPF or !EEE 1801 power intent definition file? Do you need to reduce leakage and dynamic power? We have just released several training videos that can answer many of your low-power questions. The newly released videos...

This blog discusses the different Voltus electrostatic discharge (ESD) checks in the form of rules to ensure your design is protected against ESD.

You put your design through a multitude of tools for various transformations. Going back to formal verification in between every change to rely on your simulation tools can be a rigorous approach, but wait... there is an easier way: Use equivalence checking, with Conformal® Equivalence Checker. And that easier way is made even easier with these videos on how to do your equivalence checking, along with a few of...

Do you have a requirement to specify measurements that are not default while performing memory characterization? Liberate MX has a solution for you.

With advanced-process nodes, a standard cell's physical delay, net delay, and congestion all lead to a higher netlist requirement. Genus/Innovus iSpatial bridges synthesis and implementation with integrated core engines and unified physical optim...

This blog post outlines four simple steps for analysis of your electrostatic discharge (ESD) protection circuitry using the Voltus ESD Analysis solution.

The hustle bustle of the cities is only an example of the external noise, which we are aware of through the obvious observations of our sensory organs. However, in terms of electronics, a noise maybe defined as any kind of unwanted signal that interferes with the real signal in a timing path in a cell or circuit. Modeling of accurate noise characteristics at the cell level and being aware of the possible failures early...

Hi everyone, Are you interested in reducing the power dissipation of your design? Who wouldn’t? What about taking the advantage of Clock Gating? Clock Gating is a technique that enables inactive clocked elements to have gating logic automatical...

A blog on how the Voltus power-gating analysis solution enables engineers to address the low-power design challenge of extending battery life while reducing the leakage power.

Ever wondered what should you do if any arc, cell, or PVTs failed in a characterization run? Do you need to rerun the entire characterization process? Certainly not if you know about how to use the recovery workflow in the multi-PVT characterization flow! Read more...

"How many tape-outs have you done?" asked the design manager of a semiconductor company. My colleague and I were on a call with him to walk him through an implementation training agenda. He further explained the intent of the question “I am looking for trainer who has hands-on experience in implementing design. I want the training to be more design challenge oriented rather than just talking about command and switches...

Voltus TM IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with the full suite of design implementation and signoff tools of Cadence to deliver the industry’s fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high-performance, accuracy...