Voltus Voice: Breaking Ground with Voltus-InsightAI—A Detailed Exploration

Voltus IC Power Integrity Solution is a power integrity and analysis signoff solution that is integrated with Cadence's full suite of design implementation and signoff tools to deliver the industry's fastest design closure flow. The aim of this blog series is to broadcast the voices of different experts on how design engineers can effectively use the diverse Voltus technologies to achieve high performance, accuracy, and capacity for next-gen chip designs.

In our previous post, we unveiled the groundbreaking entrance of generative AI into the realm of electromigration and IR drop (EM-IR) analysis. Today, we're diving deeper into this exciting development by examining the intricate technologies that make AI-driven EM-IR analysis and closure possible. From the initial aggressor analysis and IR drop measurement to the IR-aware placement capabilities, we'll break down the flow behind this technology.

The Power of Aggressor Analysis-Driven Repair

In the world of IC design, preventing and repairing IR drop violations have traditionally not been straightforward processes. The IR drop violation data is derived and used to guide repairs directly addressing these issues. Yet, many times, working with IR violations directly might not yield the expected results because the violators might not be the root cause of the problem. As we venture into more advanced nodes, the game has also changed. The IR drop affecting a particular instance is no longer just an isolated event; it is increasingly influenced by the switching activities of nearby instances, known as aggressors.

This nuanced interaction between the victim and aggressor instances makes it crucial to delve deeper into their relationships when an IR drop violation occurs. Instead of merely applying blanket repairs on the reported IR violations, it is now essential to identify the precise root cause of the IR drop and determine an appropriate mitigation method.

The following image shows the victim-aggressor relationship and aggressor impact heat map:

While an IR drop aggressor has the potential to cause an IR drop violation in a nearby victim instance, it does not necessarily be an IR violation itself. Interestingly, many aggressors that contribute to these violations are not IR drop violations, as shown below:

The repair methodologies typically focus on fixing instances where IR drop violations are detected, overlooking these aggressors. This oversight can lead to inefficient and incomplete repair strategies, as the aggressors remain unaddressed, continuing to cause issues down the flow. Unlike traditional IR drop repair tools, Voltus InsightAI leverages an intelligent aggressor analysis engine to dive into the core issue. It does not merely flag violations; it sets the proper repair priorities, makes the necessary tradeoffs, and selects the most efficient and effective repair method.

Next-Gen IR Drop Measurement: A Fresh Perspective

Conventionally, the IR drop state in circuit designs has been measured using two primary parameters: the Worst IR drop Violation (WIV) and the Number of IR Violation counts (NIV). While these metrics provide some insights, they fall short of offering a comprehensive picture of the actual IR drop state. For instance, consider the two scenarios where both designs have identical WIV and NIV values.

Despite these similarities, the overall distribution of IR drop can be vastly different in each case. On the surface, they might appear to be equally problematic. However, one design might have its violations clustered in a critical area, posing a significant risk, while the other might have them spread out more evenly, posing a less immediate threat.

In Voltus InsightAI, we introduce a new IR drop parameter, the Total IR Drop Violation (TIV) parameter. TIV is an advanced metric that sums up all the IR drop violations in a design based on a user-defined IR drop threshold. This powerful parameter, combined with WIV and NIV, enables designers to achieve an unprecedented level of accuracy in assessing the IR state of their designs. This trio of metrics aligns seamlessly with the traditional metrics used to evaluate a design's timing state, such as Worst Negative Slack (WNS), Total Negative Slack (TNS), and Number of Violating Paths (NVP). In essence, we are bringing the same rigor and clarity to IR drop analysis that has long been a standard in timing analysis.

An Introduction to the Voltus InsightAI Flow

The Voltus InsightAI flow is designed to enhance the Innovus Place and Route (P&R) implementation by addressing the potential issues arising from IR drop. This evolved flow consists of two primary repair steps seamlessly integrated into the overall design.

• First, the Pre-Route IR fixing step tackles IR drop repair and prevention right after the Clock Tree Synthesis (CTS) phase. This step ensures that any potential IR drop issues are mitigated early on, setting a solid foundation for the subsequent routing stages.
• Next, the Post-Route IR fixing step comes into play. This step focuses on the post-route optimization database, further fine-tuning and repairing any IR drop issues that may have emerged during the routing process.

By addressing these issues at both the pre- and post-route stages, the Voltus InsightAI flow ensures a robust, reliable design, paving the way for higher performance and efficiency in the final design.

The following diagram illustrates the Voltus InsightAI flow:

The following are the five new functionalities designed for the Voltus InsightAI flow:

1. Pre-route RPG (reinforce PG) - improves critical PDN weakness points by inserting additional wires and vias to augment the existing PG grid.
2. get_ir_insight – bridging between Innovus and Voltus, it utilizes the Voltus IR drop analysis data to perform root cause analysis, violation categorization, repair method assignment, and repair directive generation for Innovus to perform the actual design changes. While being the main driver of the Voltus InsightAI flow, get_ir_insight can also be used as a standalone IR drop analysis and debugging tool, allowing designers to perform their own root cause analysis.
3. IRAP (IR-aware placement) - reduces the impact of aggressors by spreading out cells.
4. Post-route RPG - optimizes post-route PDN using the available routing tracks.
5. IR-ECO - performs aggressor impact reduction by aggressor sizing.

A Case in Point

The following example is a comparative analysis of the results for vectorless and vector-based signoff data:

• Comparison with vectorless signoff
  • WIV improvement from 285.2mV to 208.7mV
  • TIV improvement from 4464.34V to 110.43V
  • NIV improvement from 21398 to 707
• Comparison with vector-based signoff
  • WIV improvement from 302.1mV to 258.3mV
  • TIV improvement from 5059.71V to 585.615V
  • NIV improvement from 13226 to 1330

The following figures illustrate the histogram and heat maps between the baseline flow and Voltus InsightAI flow:

Voltus InsightAI Recap

In conclusion, Voltus InsightAI emerges as a powerful ally for designers navigating the complexities of power integrity. By enabling multiple optimization technologies such as early rail analysis on incomplete P&R designs, IR-aware placement, and power-grid reinforcement, designers can effectively enable fast, automated IR drop closure and enhanced productivity.

About Voltus Voice

"Voltus Voice" showcases our product capabilities and features and how they empower engineers to meet time-to-market goals for the complex, advanced-node SoCs that are designed for next-gen smart devices. In this monthly blog series, we also share important news, developments, and updates from the Voltus space.

Learn more about Cadence's digital design and signoff products and services.