Addressing Sequential Elements Optimization in the VLSI Chip Design

12 Feb 2025 • 3 minute read

With highly advanced technology, the real designs are getting complex, making the design optimization process complicated and comprising the design results. The sequential cells play a vital role in the chip's optimization and functioning.

Constant, merged, and unused flops, among other factors, impact the chip design's power, performance, and area (PPA) during the synthesis stage. Is there any way to handle the flops optimization for the best PPA results?

The solution lies with the Cadence Genus Synthesis Solution. The ultimate goal of the Genus Synthesis Solution is very simple: deliver the best possible productivity and Power, Performance, and Area (PPA) during register-transfer-level (RTL) logic synthesis of the chip.

How do you manage the flop optimization?

Unused registers on selected modules
Disabling sequential merging
Optimizing constants on specific flops
Preventing register deletion
Preventing Selective registers during elaboration
Preventing merging of specific flops

Do you want to know how Genus Synthesis Solution manages all these? Explore the videos that cover how to control or enable/disable the optimization of registers or sequential elements in Genus. You can refer to the videos on the ASK Portal (Cadence login required).

Video Links

Removing Unused Registers on Selected Modules in Genus Synthesis Solution (Video)

Preventing Register Deletion in Genus Synthesis Solution (Video)

Disabling Sequential Merging in Genus Synthesis Solution (Video)

Preventing Merging of Specific Flops in Genus Synthesis Solution (Video)

Preserving Selective Registers During Elaboration in Genus Synthesis Solution (Video)

Optimizing Constants On Specific Flops in Genus Synthesis Solution (Video)

Related Resources

Video Links: Enhance your knowledge of Genus and Joules with short videos

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Explore the one-stop solution product pages on the Application Support and Knowledge Portal (Cadence login required).

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