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Whiteboard Wednesdays - The 4 Steps Necessary for an Effective Cloud-Based Design Strategy

By Corrie Callenbach | 21 May 2019

In this week's Whiteboard Wednesdays video, Craig Johnson identifies the 4 steps to follow to create an effective strategy for moving electronic design work to the cloud. Skip one of these and your results could be disappointing. https://youtu.be/rKoatyYa35E

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Whiteboard Wednesdays | Cloud-based Design | cadence cloud
Whiteboard Wednesdays - Featuring the new Tensilica Vision Q7 DSP IP for Vision and AI

By Corrie Callenbach | 15 May 2019

In this week’s Whiteboard Wednesdays video, Pulin Desai talks about the latest addition to the Vision DSP family, the Vision Q7 DSP. The Vision Q7 DSP offers up to 1.7X higher TOPS in the same area as Vision Q6 DSP. The Vision Q7 DSP provides 2X greater AI and floating-point performance compare to Tensilica Vision Q6 DSP. It is also optimized for simultaneous localization and mapping (SLAM) through instruction and architectural...

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Whiteboard Wednesdays | Vision Q7 DSP
Whiteboard Wednesdays - Limitations of Scan Compression QoR

By Corrie Callenbach | 7 May 2019

In this week's Whiteboard Wednesdays video, Scan Compression reduces the digital IC test time and data volume by orders of magnitude, but the technology’s limitations prevent achieving higher compression ratios. Distinguished engineer Rohit Kapur explains the different limiters of compression QoR and impact on scan design. To learn about the Cadence Modus DFT Software Solution, visit the product page at https://www.cadence...

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Whiteboard Wednesdays | modus | Scan Compression
Whiteboard Wednesdays - SIMD Capability of B10 B20 and Some Associated Vector Processing Units

By Corrie Callenbach | 30 Apr 2019

In this week's Whiteboard Wednesdays video, Pierre-Xavier Thomas shows some of the processing units of the B10/B20 supporting the SIMD architecture in the context of the operator support. https://youtu.be/-620ZPxaYf8

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Whiteboard Wednesdays | ConnX
Whiteboard Wednesdays - Scan Compression Fundamentals

By Corrie Callenbach | 23 Apr 2019

In this week's Whiteboard Wednesdays video, Industry expert Rohit Kapur introduces the basic concepts of digital IC scan compression. Topics explained include the impacts of test application time and test data volume on test cost and the problems solved by implementing scan compression. To learn about the Cadence Modus DFT Software Solution, visit the product page at https://www.cadence.com/modus www.youtube.com/watch...

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Whiteboard Wednesdays | modus | Scan Compression
Whiteboard Wednesdays - CloudBurst - Fast, Painless, Proven Solution for Hybrid Cloud Environments

By Corrie Callenbach | 16 Apr 2019

In this week's Whiteboard Wednesdays video, Craig Johnson explains the reasons behind the addition of the CloudBurst Platform to the Cadence® Cloud Portfolio and its usefulness in serving peak demand in hybrid cloud environments. https://youtu.be/TjlOTW31fkE

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Whiteboard Wednesdays | Cloud-based Design | cloudburst
Whiteboard Wednesdays - 3X Faster Design Closure with Quantus Integrated Virtual Metal Fill

By Corrie Callenbach | 9 Apr 2019

In this week's Whiteboard Wednesdays video, Senior Product Engineering Manager Varun Raj Garapati outlines why traditional metal fill insertion, usually at the signoff stage, is not recommended for FinFET designs to ensure fastest design closure. The Quantus Integrated Virtual Metal Fill (IVMF) solution offers designers the ability to run virtual metal fill much earlier in the design during post-route optimization stage...

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Whiteboard Wednesdays | Quantus | IVMF
Whiteboard Wednesdays - When it Comes to Cloud-Based Design, One Size does Not Fit All

By Corrie Callenbach | 2 Apr 2019

In this week's Whiteboard Wednesdays video, Tom Hackett describes how different types of companies possess different combinations of 3 key assets needed for successful cloud-based electronics design. Since their assets are different, the solutions they need for cloud-based design are also different. https://youtu.be/RVSlR8ZPRuo

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Whiteboard Wednesdays | Cloud-based Design | cadence cloud
Whiteboard Wednesdays - FMCW Radar Receiver Signal Processing Using ConnX B20 DSP

By Corrie Callenbach | 26 Mar 2019

In this week's Whiteboard Wednesdays video, Ramchandra Dabade talks about FMCW radar receiver processing use case and highlights the relevant ConnX B20 features used for different signal processing blocks of the FMCW radar receiver chain. https://youtu.be/doaFix2DL_0

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DSP | Whiteboard Wednesdays | radar signal processing | ConnX
Whiteboard Wednesdays - 5G PHY Use Cases on B20

By Corrie Callenbach | 19 Mar 2019

In this week's Whiteboard Wednesdays video, Rong Chen talks about the 5G use cases and PHY processing and highlights the B20 DSP features which enable efficient control and DSP processing for 5G modem design. https://youtu.be/TIVHPZr1WVA

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5G | B20 | Whiteboard Wednesdays | ConnX
Whiteboard Wednesdays - Solving Scan Compression Congestion Issues with Modus 2D Elastic

By Corrie Callenbach | 12 Mar 2019

In this week's Whiteboard Wednesdays video, Rohit Kapur, Distinguished Engineer at Cadence Design Systems, discusses the topic of scan compression and the layout problems created as compression ratios grow. The Modus DFT Software Solution targets this impact using its patented physically aware 2D Elastic Compression architecture, without any impact on fault coverage or chip size. For more information, read the datasheet...

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Whiteboard Wednesdays | modus | Scan Compression
Whiteboard Wednesdays - Diagnostics – What Makes Modus Diagnostics an Industry Leading Tool

By Corrie Callenbach | 5 Mar 2019

Cadence distinguished engineer Rohit Kapur introduces diagnostic capabilities in IC testing. Kapur explains the metrics used to evaluate diagnostics tools and discusses why the Cadence Modus DFT Software Solution is the industry-leading solution. For more information, please visit www.cadence.com/modus https://youtu.be/Q-j1t64DwoU

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Whiteboard Wednesdays | modus
Whiteboard Wednesdays - Evolution of the ConnX Family with B10 and B20

By Corrie Callenbach | 26 Feb 2019

In this week’s Whiteboard Wednesdays, Pierre-Xavier Thomas introduces the B10 and B20 as a complement to the ConnX family with higher performance and additional features to support new wireless communications standard and high-resolution radar/lidar applications. https://youtu.be/MaWYNbOEbMo

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Whiteboard Wednesdays | ConnX
Whiteboard Wednesdays - An Introduction to IC Test and Modus

By Corrie Callenbach | 20 Feb 2019

In this week's Whiteboard Wednesdays video, distinguished Engineer Rohit Kapur introduces the concept of scan testing and gives an overview of the Modus DFT Software Solution and Genus Synthesis Solutions from Cadence. Learn the basic steps of Design for Test (DFT) including scan design, test pattern generation (ATPG), and fault simulation. For more information, read the datasheet and visit the product page at www.cadence...

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DFT | Whiteboard Wednesdays | modus | Test
Tensilica HiFi 5 DSP Enabling Machines for Voice UI

By Corrie Callenbach | 13 Nov 2018

In this week’s Whiteboard Wednesday, Sachin Ghanekar, Design Engineering Group director at Cadence, talks about the Cadence® Tensilica® HiFi 5 DSP, and how it works to fill the needs of both front-end processing and neural networks. www.youtube.com/watch

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hifi 5 | Whiteboard Wednesdays | Tensilica | HiFi DSP
Whiteboard Wednesdays - How the Cadence 112G SerDes IP Solves the Challenges of Long-Reach Signaling

By Corrie Callenbach | 6 Nov 2018

In this week’s Whiteboard Wednesday, Wendy Wu explains what NRZ and PAM-4 signaling is all about and the sources of channel loss that make high-speed, long-reach SerDes design so challenging. She then describes the unique architectural advantages of the Cadence® 112G Long-Reach SerDes IP that makes it an ideal choice for high-speed networking and server chip designs. https://youtu.be/s_kZBbbf110

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Whiteboard Wednesdays | 100G Ethernet | 112G SerDes | PAM-4 | SerDes | 400G Ethernet | 800G Ethernet
Whiteboard Wednesdays – Machines with Voice UI and Tensilica HiFi 5 DSP

By Corrie Callenbach | 31 Oct 2018

In this week’s Whiteboard Wednesdays video, Sachin Ghanekar talks about the new Tensilica HiFi 5 DSP, the first DSP optimized for AI speech and audio processing. This fifth-generation HiFi DSP offers 2X audio processing and 4X neural network (NN) processing improvements versus its predecessor, making it ideal for voice-controlled user interfaces in digital home assistants and automotive infotainment. www.youtube.com...

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Whiteboard Wednesdays | HiFi DSP | neural networks
Whiteboard Wednesdays - Cadence Unveils 112G Long-Reach SerDes IP in 7nm Technology

By Corrie Callenbach | 24 Oct 2018

With hyperscale datacenters requiring network switches delivering bandwidths of 12.8 Tbps and beyond, there is strong demand for 112G SerDes IP for the underlying ASICs and SoCs. In this week’s Whiteboard Wednesday, Wendy Wu explains the high-performance networking market drivers and introduces the Cadence® 112G Long-Reach SerDes IP implemented in 7nm process technology. www.youtube.com/watch

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Whiteboard Wednesdays | 100G Ethernet | 112G SerDes | PAM-4 | 400G Ethernet | 800G Ethernet
Whiteboard Wednesdays - Tensilica Neural Network Compiler: An Offline Tool for Efficient Deployment of Neural Networks

By Corrie Callenbach | 9 Oct 2018

In this week’s Whiteboard Wednesda ys video, Megha Daga describes how the Tensilica Neural Network Compiler works, from a trained floating - point network to an optimized source code generation for a Tensilica AI-enabled DSP or processor. https://youtu.be/V9BV_BLIUiI

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DSP | Whiteboard Wednesdays | Tensilica | neural networks | AI
Whiteboard Wednesdays - Significance of Sparsity in Neural Networks

By Corrie Callenbach | 2 Oct 2018

In this week’s Whiteboard Wednesdays video, Megha Daga discusses how handling sparsity positively affects bandwidth, performance, and power efficiency. https://youtu.be/pgouTDPhjlQ

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Whiteboard Wednesdays | convolutional neural networks | neural networks | CNN
Whiteboard Wednesdays - Standalone AI Processor: Tensilica DNA 100 Processor IP for On-Device AI

By Corrie Callenbach | 19 Sep 2018

In this week's Whiteboard Wednesdays episode, Megha Daga describes the new Tensilica DNA 100 Processor IP for on-device AI. This AI processor delivers industry leading high performance and power efficiency across a full range of compute from 0.5 to 100s of TMACs and is well suited for on-device neural network inference applications. https://youtu.be/eT4f2CoBByo

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Whiteboard Wednesdays | dna 100 | AI
Whiteboard Wednesdays - What You need to Know About ISO26262-2018 2nd Edition

By Corrie Callenbach | 4 Sep 2018

In this week's Whiteboard Wednesdays video, the first in a multi-part series, Scott Jacobson explores the changes in the upcoming ISO26262-2018 standard update and how they affect semiconductor design. https://youtu.be/QFV3KIUwJxs

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Whiteboard Wednesdays | ISO 26262
Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 2

By Corrie Callenbach | 28 Aug 2018

In this week's Whiteboard Wednesday, Tom Hackett continues his explanation of neural network basics using an Excel spreadsheet as a learning vehicle. You can download the spreadsheet here: https://ip.cadence.com/uploads/1213/neural-network-calculator-xlxs-zip https://youtu.be/ow1ZuOPD72I

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Whiteboard Wednesdays | neural networks
Whiteboard Wednesdays - The Simplest Neural Network Explanation Ever - Part 1

By Corrie Callenbach | 22 Aug 2018

In this week's Whiteboard Wednesday, Tom Hackett explains neural network basics using an Excel spreadsheet as a learning vehicle. You can download the spreadsheet here: https://ip.cadence.com/uploads/1213/neural-network-calculator-xlxs-zip https://youtu.be/YAaC94Ke2Ls

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Whiteboard Wednesdays | neural networks
Whiteboard Wednesdays - Von Neumann's 5 Bottlenecks and CCIX - Part 2

By Corrie Callenbach | 31 Jul 2018

In this week's Whiteboard Wednesdays video, Tom Hackett completes the story of the evolving von Neumann computer architecture and the adaptations driven by recent cloud computing challenges. The effort to overcome these challenges has led to the development of a new industry standard called the Cache Coherent Interconnect for Accelerators (CCIX). https://youtu.be/D8pzVq4uJ-E

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Whiteboard Wednesdays | ccix | cloud