Whiteboard Wednesdays - Low Power SoC Design with High-Level Synthesis - Whiteboard Wednesdays - Cadence Blogs

29 Apr 2020

Whiteboard Wednesdays - Low Power SoC Design with High-Level Synthesis

In this week’s Whiteboard Wednesdays video, Dave Apte discusses how to create the lowest power design possible by using architectural exploration and Cadence’s Stratus HLS solution.

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Whiteboard Wednesdays - Low Power SoC Design with High-Level Synthesis