Whiteboard Wednesdays Blogs

In this week's Whiteboard Wednesdays video, Senior Product Engineering Manager Varun Raj Garapati outlines why traditional metal fill insertion, usually at the signoff stage, is not recommended for FinFET designs to ensure fastest design closure. The Quantus Integrated Virtual Metal Fill (IVMF) solution offers designers the ability to run virtual metal fill much earlier in the design during post-route optimization stage to reduce ECOs for faster design closure. IVMF functionality is available both in-design in the Innovus environment or as a standalone signoff version. To learn more about the Cadence Quantus Extraction Solution, visit https://www.cadence.com/go/quantus-ex.... Don’t Emulate—Virtualize Metal Fill!