Cadence Adds 10 New VIP to Strengthen Verification IP Portfolio for AI Designs

21 Nov 2025 • 1 minute read

Cadence has unveiled 10 Verification IP (VIP) for key emerging interfaces tuned for AI-based designs, including Ultra Accelerator Link (UALink), Ultra Ethernet (UEC), LPDDR6, UCIe 3.0, AMBA CHI-H, Embedded USB v2 (eUSB2), and UniPro 3.0. These new VIP will streamline the verification process for engineers to ensure their designs meet the latest industry standards with high quality and fast time to market.

Cadence VIP are trusted by hundreds of customers. They offer a comprehensive verification solution for the most complex protocols, along with a UVM SystemVerilog test suite that speeds up bring-up time and enables bug detection from day one.

“The fast-evolving AI market creates a new level of requirements for higher bandwidth and lower power, resulting in a new set of interfaces to address these needs,” said Ziyad Hanna, Corporate VP at Cadence. “Cadence is committed and proud to provide the Verification IP and tools to enable the new generation of AI SoCs.”

More details of the new VIP can be found at the individual product pages:

The new VIP solutions are part of the broader Cadence verification full flow, which includes Palladium Z3 emulation, Protium X3 prototyping, Xcelium simulation, Jasper Formal Verification Platform, Helium Virtual and Hybrid Studio, and Verisium AI-Driven Verification Platform. The Cadence verification full flow offers unparalleled verification efficiency, maximizing the number of bugs detected while minimizing the cost and time invested per day.

Learn more about the Cadence VIP Portfolio.