UCIe Full Signal Integrity Analysis Flow

The increasing complexity and computational demands of 3DHI systems design are challenging. On-package chiplets demand significant simulation and increasing design turns, as more designs are packaging multiple components, which only a few years ago were discretely packaged. The disparate and deep skillsets of these technologies and the exponentially increasing computational demands of newer process nodes threaten to lengthen design times and increase time-to-market ramps.

UCIe Standard

The Universal Chiplet Interconnect Express (UCIe) standard is important for the future of advanced packaging and semiconductor system design. UCIe Full Signal Integrity Analyis with Compliance Check for Heterogenous Integration, presented at the 2026 International Conference & Exhibition on Device Packaging (IMAPS) by Shawn Mills and Ken Willis of Cadence, explores the trends in the industry and overviews Cadence’s complete analysis solutions with UCIe standard compliance checking and verification.

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Cadence UCIe Compliance Kit

The Cadence UCIe compliance kit uses a novel approach for signoff verification. This paper details the analysis solution and design architecture with various test cases from Cadence and its customers. The paper includes the following sections: details about the UCIe standard and its importance,  heterogeneous integration of the interposer, and lastly, the fine-grained simulations and analysis required to close the design.

The complete paper, recently published in Advancing Microlectronics, is now available to read. More information on Cadence’s UCIe interface can be found in a Cadence webinar case study, How to Sign Off Your UCIe Interface.