Cadence CEO Outlines the Path to the CMOS 2.0 Era at IMEC ITF World 2026

At this year's ITF World 2026 in Antwerp, Belgium, global technology leaders gathered to discuss one of the industry's defining questions: how semiconductor innovation continues to scale in an era increasingly shaped by artificial intelligence. The annual event brought together executives and researchers across the semiconductor ecosystem, including participants from NVIDIA, Arm, Samsung, TSMC, and ASML, reflecting the industry's growing focus on next-generation system architectures and AI-driven innovation.

On the first day of the event's morning program, Dr. Anirudh Devgan, president and CEO of Cadence, presented a vision focused on "Powering the AI Supercycle: AI-Driven Design for the CMOS 2.0 Era." His presentation focused on a major shift now taking place across semiconductor development: AI is no longer simply a workload requiring more compute power; it is increasingly becoming an essential technology for designing the systems that enable that compute.

The session was built around a central theme: Design for AI and AI for Design.

Design for AI addresses the growing demand for semiconductor and system architectures optimized for increasingly complex AI workloads. AI models continue to scale in size and capability, placing pressure on traditional approaches to performance and energy efficiency. At the same time, AI for Design introduces AI-driven methods directly into electronic design automation (EDA) and system design workflows, enabling engineers to manage a level of complexity that is increasingly difficult to address with conventional approaches.

Dr. Devgan argued that the industry is moving beyond an era defined largely by transistor scaling and into one characterized by system-level optimization. As architectures evolve toward heterogeneous integration, chiplets, 3D stacking, and emerging device structures, design decisions can no longer be addressed in isolation.

"The challenge is no longer optimizing only the chip," the session suggested. "It is optimizing across the entire stack."

This broader challenge is driving greater attention toward Cross-Technology Co-Optimization (XTCO)—an approach that simultaneously considers interactions across electrical, thermal, power, memory, compute, and mechanical domains. Rather than sequential optimization between independent design stages, XTCO introduces concurrent, multidomain exploration across technologies and system layers.

That transition becomes especially important as the industry enters what Dr. Devgan characterized as the CMOS 2.0 era.

CMOS 2.0 extends semiconductor scaling beyond traditional geometric shrink approaches and toward heterogeneous, vertically integrated architectures. Future systems are expected to incorporate angstrom-scale devices, complementary field-effect transistor (CFET) architectures, advanced packaging technologies, and tightly integrated 3D structures.

The implications for design are substantial.

Design flows must now manage dramatically higher levels of complexity, including billions of transistors, hundreds of IP blocks, massive interconnect structures, and multiphysics interactions spanning thermal, electrical, and mechanical domains. According to the presentation, these challenges increasingly require autonomous and AI-driven design methodologies to sustain future scaling.

The session also highlighted Cadence's expanding work in agentic AI through its Super Agent framework. Rather than functioning as isolated AI assistants, these systems were positioned as orchestrated design agents capable of combining large-language-model reasoning with domain-specific EDA workflows, design intent, specifications, and historical project data. The objective is to move from point-tool optimization toward coordinated exploration across digital, analog, implementation, signoff, and system analysis stages.

Dr. Devgan also highlighted the long-standing collaboration between Cadence and IMEC, which spans more than fifteen years and includes work ranging from advanced-node pathfinding and 3D-IC reference flows to silicon photonics and CFET research. As design challenges continue to increase in scale and complexity, he noted the importance of continued industry alliance to develop solutions that can analyze, understand, and optimize across domains, workloads, and system scales. Cadence continues to invest in its partnership with IMEC and the broader ecosystem to address these evolving challenges and enable the next generation of semiconductor and system innovation.

One example presented involved joint Cadence – IMEC work on CFET architectures at the A7 technology node, demonstrating substantial block-level area scaling improvements compared with current-generation baselines. While still emerging, the results point toward the role new device architectures could play in extending semiconductor scaling into future generations.

"We are entering a new era of computing where the limits of traditional scaling give way to a profound reinvention of silicon and systems. AI is not just accelerating demand; it is redefining how technology is designed and delivered. Through our deep partnership with imec, we are pioneering Cross-Technology Co-Optimization (XTCO) to unify innovation across every layer of the stack. By harnessing physics-grounded AI agents to explore vast, multi-dimensional design spaces, we can transcend conventional boundaries from CMOS 2.0 devices to system architecture, unlocking a new frontier of compute performance, efficiency, and intelligence."

- Anirudh Devgan, President and CEO, Cadence

Perhaps the broader message of the session was that AI's impact on semiconductors is becoming bidirectional. Industry is building increasingly advanced AI systems, while AI itself is becoming integral to how those systems are conceived and developed.

As the AI supercycle continues to reshape computing, the future may depend less on advances in any single technology layer and more on how effectively the entire stack—from materials and devices to systems and design tools—can be optimized together.

Learn more about Cadence's Design for AI and AI for Design strategy.