Intelligent Custom Signoff Closure with the Quantus Insight Solution

11 Feb 2025 • 2 minute read

Running inside the Virtuoso Platform, the Quantus Insight Solution offers unique capabilities to analyse and mitigate layout parasitics in custom layout design. Particularly at advanced nodes, interconnect RCs can strongly affect design performance and power.

Engineered for handling large DSPF files, the Quantus Insight Solution offers a comprehensive array of analyses featuring rapid root cause identification, a what-if explorer for manipulating individual parasitic components, and the capability to export experimental DSPF/I-DSPF files for re-simulation. Intuitive visualization, user-friendly GUI, and remarkable performance make the Quantus Insight Solution an indispensable asset for designers—accelerating design closure turnaround time.

Please join me, Justas Lukosiunas, Lead Application Engineer, for this webinar that uses real-life design examples to introduce key Quantus Insight Solution concepts and capabilities—highlighting how the tool can significantly boost productivity in custom IC layout signoff closure.

Date and Time

Wednesday, March 05, 2025
09:00 GMT London/10:00 CET Munich/11:00 IST Jerusalem/14:30 IST Bangalore/17:00 CST Beijing

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Like this topic? Take this opportunity and register for the free online course related to this webinar topic: Quantus Transistor-Level T1: Overview and Technology Setup Training Course | Cadence

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