Excuse the tennis analogy, but just coming out of Wimbledon! However, EDA and academia have had a long-standing tennis match, if you will, in which there is a "give and take" between the EDA world and the many universities around the world. At Cadence, we have an extensive University Program and, through the years, we have worked closely on everything from developing curriculum (using our software, of course) to engaging universities in specific research for us to assisting Ph.D. students with the work on their theses. In fact, the Design Automation Conference (DAC) has had a university arm from the earliest days of the conference. This brings me to the reason for this blog, to congratulate Carnegie Mellon University Ph.D. student Shupeng Sun for receiving the newly established Best Poster Award at the ACM SIGDA Ph.D. Forum at this year's DAC in San Francisco. The poster focused on Sun's radically new statistical analysis methodology that will allow companies to produce better circuits in electronic devices.
The reason it is of particular interest to me is that the work was a collaborative project between CMU and Cadence. A number of Cadence researchers and developers also have been involved in the project, including engineering directors Hongzhou Liu and Ben Gu, and Kangsheng Luo, a senior member of the technical staff.
All electronics are made up of thousands or even millions of circuit blocks, each of which can contain thousands of transistors — and if one of these blocks fail, the electronic device will not function properly. As electronics become more complicated, more circuit blocks are needed, increasing the chance for failure.
"If you only have 10 circuit blocks, it is relatively easy to make all 10 work, but if you have one million circuit blocks, then it is more difficult to make all of them work," said ECE Associate Professor Xin Li, Sun's adviser and research colleague.
Before Sun's novel work, validating a circuit block involved running a computer simulation that produces sample circuit blocks. Each sample can take minutes to hours to simulate, and millions of samples are required for an accurate validation of a new design. This method is very costly because it can take a few weeks or months to run one validation. And if the original design does not work, a second validation must be run — an enormous problem if a circuit designer has a deadline. Because the simulation process is so laborious, most companies opt for a very simple, very inaccurate estimation.
Sun developed an algorithm that calculates the failure rate and accounts for variability and uncertainties in the manufacturing process, allowing companies and researchers to run significantly fewer simulations. This new statistical methodology, referred to as Scaled-Sigma Sampling (SSS), requires producing only a few hundred or thousand samples.
"A few of the world's top semiconductor companies are already evaluating this new algorithm, and we are in the process of integrating it with our commercial product, Virtuoso ADE GXL," said Glen Clark, vice president of R&D for Cadence. "This is a great example of how a university and an EDA company can work together to deliver innovative solutions for the challenging problem of memory circuit yield."
Working collaboratively with universities has been a hallmark of Cadence, and we look forward to many more interesting and fruitful adventures together. I wonder if that is what Federer said to Djokovic when they shook hands across the net? Congrats all around.