This is a topic that frequently comes up on both internal and external forums. And the answer is right in the Encounter Digital Implementation System (EDI) User Guide, but unless you already know that, you may not think to look for it there.
At some point, all of us have looked at a timing report, and reviewed the list of cells that EDI added during timing optimization. Then we wondered, "Hmmm. What does that prefix mean?" I'm sure you've seen the prefixes of the form FE_PHC, FE_RC, FE_OFC, etc. They do have specific meanings, and when debugging a timing path, it can be very helpful to know where these cells came from.
The following list is located in the EDI User Guide. It's at the end of the Optimizing Timing chapter, in a section called Default Naming Conventions.
Instance added by multi-driver net buffering
Net added by multi-driver net buffering
Instance added by DRV fixing
Net added by DRV fixing
Instance added by rebuffering
Net added by rebuffering
Instance added by critical path optimization
Net added by critical path optimization
Buffer instance added by rule-based buffer insertion
Buffer net added by rule-based buffer insertion
Instance added by hold time repair
Net added by hold time repair
Instance added by buffer insertion in optDesign -postRoute
Net added by buffer insertion in optDesign -postRoute
Instance added by postroute setuprepair
Net added by postroute setup repair
Instance created by netlist restructuring
Net created by netlist restructuring
Instance added during useful skew optimization
Hopefully this information will help you debug a timing path gone wrong, and prompt you to check out the EDI User Guide!
Here are two previous blogs related to debugging timing in EDI:
Demo: Calling Global Timing Debug for a Single Path
An Interview with Global Timing Debug Architect Thad McCracken
- Kari Summers
then what are the naming convetions used during CTS namely like (CASCADE,FENCE)
Hi Ajay, If you look in the chart, you'll see that the OFC tag can also come from optDesign. I believe these will come from fixing DRVs, like high fanout (if you have that turned on) and most likely max transition violations.
in my design huge no of buffers added with prefix FE_OFC.here what the thing is i have n't given any rule for buffer insertion.could anybody please tell me the reason for it?
Thanks for that. I find this very useful for beginners and even advanced users.