Formal verification can mean different things depending upon who you speak to. If I were blogging under Logic Design, it would probably indicate a series of loosely correlated opinions and observations on the topic of equivalency checking. However, this happens to be the Functional Verification forum and this blog about model-checking.
Model-checking: The process of checking whether a given structure is a model of a given logical formula. Or in engineer-speak, a way of automatically checking if your RTL implementation meets your design specification without a testbench.
Now that we have clearly and comprehensively established the technical context of this weekly bitstream, some disclaimers.
Next Week: Why simulation guys do not get model-checking.