Drop by the Cadence booth at DesignCon to see the latest demonstrations of Allegro PCB SI for both serial link channel analysis as well as high-speed memory interface design verification. In addition to other demos in the booth, be sure to mark your calendars for the Business Forum Panel, Do It Right or Do It Over? Signal Integrity Engineers in the Era of Highly Compressed Project Schedules where industry professionals talk about how schedule timing constraints can be just as critical as setup and hold timing.
Also, be sure to stick around for Thursday and attend the paper, New Serial Link Simulation Process, 6 Gbps SAS Case Study. Donald Telian will dicuss his engagment at Hitachi where AMI models were used with Allegro PCB SI.
Hope to see you there. Be sure to say hello.
Hi Brad, Looking forward this panel session. Should be a good one. -- Colin signal-integrity-tips.com