The use of separate force (F) and sense (S) connections (often referred to as a Kelvin connection) is a common requirement in the PCB design. The separate force (F) and sense (S) connection at the load eliminates any errors resulting from voltage drops in the force lead. The Kelvin Sense connection is routed by separating the sensing signals (S) from the lines, and delivering the power to the load (F). This type of connection prevents noise related problems in a closed loop system because it allows for more accurate measurement of the sense voltage at the load.
Consider the following figure:
A long resistive PCB trace is still used to drive the input of a high resolution Analog-Digital Converter (ADC), with low input impedance. In this case, however, the voltage drop in the signal lead does not give rise to an error, as feedback is taken directly from the input pin of the ADC and returned to the driving source. This scheme allows full accuracy to be achieved in the signal presented to the ADC, despite any voltage drop across the signal trace.
The requirement is to implement this at the schematic created using Allegro Design Entry HDL (DEHDL) to drive the PCB board created using Allegro PCB Editor so that both Force and Sense signals can be identified and constrained independently, and still allowed to be physically shorted in layout.
This flow is based on a special logical symbol, which is created and saved in a library. The force sense library symbol(s) has shorting schemes defined within the symbol definition, which allows the engineer to seamlessly define the nets to be force sense. When placed in a schematic, the shorting scheme will short at least two sense lines to a force line. While packaging the schematic, separate nets are generated for the Sense and Force lines which are passed on to the PCB board file. As shown in the image below, four sense lines are connected to a force line using the library symbol. Inside PCB Editor, a symbol gets placed, and defines the location of the short for force and sense signals.
The pins of the schematic symbol will have a unique property called PIN_SHORT whose value consists of the logical pin names. While packaging the schematic (running File > Export Physical), based on the <project>.CPM directive, the Packager-XL(PXL) acknowledges the PIN_SHORT property value and creates a NET_SHORT property with the value containing the physical net names connected to the logical pin names.
When you look at the PCB Editor DRA symbol for the footprint, you will see that the pins with different pad stacks are placed at the same location.
This flow allows for individual net constraints to be assigned and used in the front to back flow. As an example, Max Propagation Delay and trace width can be defined.
Refer the following AppNote for the detailed procedure used to implement the Force-Sense (Kelvin) connection using Allegro Design Entry HDL (DEHDL) & Allegro PCB Editor.
Click here for the AppNote.
Note: The above link can only be accessed by Cadence customers who have valid login credentials for Cadence Online Support (http://support.cadence.com).
Cadence Customer Support
Hello, when I export in allegro it don't export PIN_SHORT property in NET_SHORT in allegro but keep PIN_SHORT property. Why Thanks
Enhancement request refused. This feature will not be available in captur CIS. I include the response from customer support below: Regarding SR 43072588, "Add PIN_SHORT attribute for force-sense Kelvin connections." I wanted to inform you that your Cadence Change Request (1055822) number Service Request 43072588 status has been changed.
The new status is set to Inactive, which means that no action is planned. Each CCR is carefully considered, evaluated, and prioritized along with other fixes, planned feature additions, and enhancement requests, for possible inclusion in upcoming product updates and releases.
If you feel this is very important and would like us to reconsider, respond to this message and the AE working on your SR will be in contact with you.
Currently PIN_SHORT attribute is specific to Allegro Design Entry HDL - Allegro PCB Editor flows. It is not implemented in the Capture CIS product and we currently have no plans to implement this feature in Capture CIS. If you feel this feature would enhance your flow using Capture CIS, please use http://support.cadence.com and submit an enhancement request so that this can be considered while planning for a future release.
Could you tell me if there is any plan to port this functionality to design Capture CIS?
Thanks for your comment. The AppNote specified in this blog is valid if you are using Allegro Design Entry HDL (DEHDL) as a schematic editor & Allegro PCB Editor for the board layout. If you are having issues installing PSpice on your system, please file a support ticket using the link http://support.cadence.com and a representative from Cadence will assist you with your issue.
I try down load PSpice Schematics Installer but the my laptop keep saying no SPB 16.5 installation found exit set up...can you please help show me how to do..Thanks very much.