The signal integrity (SI) prophets had predicted this time would come, and it turns out they were right. The techniques that SI engineers have been using for the past decade to analyze multi-gigabit serial link interfaces are now starting to be applied to parallel memory interfaces, such as DDR4. And it all makes sense.
Back when PCI Express initially came out at 2.5Gbps, we saw a seismic shift in how simulation and analysis would be done, forever changing the SI landscape. The requirement to evaluate eye diagrams derived from huge bit streams of 10,000 bits or more pushed traditional circuit simulation into a characterization role, and convolution-based channel simulators came on the scene to handle the new high-capacity simulation needs. The need to efficiently model equalization effects, including real-time adaptation, gave rise to executable "algorithmic" models, and a new capability called "AMI" for "Algorithmic Modeling Interface" was driven into the industry-standard IBIS specification. Those were exciting times in the SI world, and Cadence was out in front leading the pack (see Interrogating the chips in this 2007 EE Times article).
Serial link analysis techniques such as bit error rate (BER) with bathtub curves, high-capacity simulation, and eye diagrams are now part of memory interface analysis.
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Now we have fast-forwarded into a new era, and the memory interfaces we are dealing with today are looking eerily "serial linkish". The data rates we see for DDR4 data buses today are right where we were initially for PCI Express. DDR4 I/O structures are similar to what we have historically had in the SerDes space, with built-in pullup termination on-die, and nicely linear, symmetric, well-behaved output impedances. While signaling is still single-ended, data buses have moved closer towards point-to-point topologies, with more use of "clamshell" component placement on top and bottom of the PCB to cluster loads at the end of the transmission line when possible. And while equalization has still eluded off-the-shelf memory devices (largely for cost reasons), on the controller side of the interface we are seeing feed-forward equalization (FFE, i.e. pre/de-emphasis) becoming more and more common.
In addition to taking on serial link characteristics, the techniques used to analyze DDR4 are also shifting towards those traditionally used in serial links. Data bus compliance and timing for DDR4 has shifted from traditional cycle-by-cycle setup and hold criteria to a mask-based compliance, as commonly used with SerDes devices and serial links. Also, DDR4 JEDEC specs now specify a target BER; "The design specification is BER <1e-16 ... BER will be characterized and extrapolated if necessary using a dual dirac method ..." These are exactly the same types of specifications that serial link interfaces have been using for years.
So where does all of this lead us? Cadence Sigrity SystemSI - Parallel Bus Analysis has integrated the serial link channel simulation engine in, and successfully applied it to coupled, single-ended parallel buses, even including non-ideal power effects (patent pending). What does this bring us? First, it brings us simulation capacity, so you now have the unique ability to run hundreds of thousands or even millions of bits of traffic through the memory interface, way beyond the capacity of traditional circuit simulation. This lets you see what the eye is really going to look like in the lab, when you are sampling many, many bits worth of data on your oscilloscope. This also enables deterministic and random jitter to be injected, so you can see what effect that will have on the eye.
AMI modeling comes along for the ride as well. Once channel simulation is introduced, you are also free to use AMI models for the equalization used at the controller. FFE modeling used with serial link applications can be directly leveraged for controller equalization, and comprehensive AMI models are included with Sigrity SystemSI.
But fundamentally what all this simulation capacity and modeling enables is generation of a very detailed eye distribution, from which (with dual dirac statistical post-processing) bathtub curves can be produced, just like with serial links. The bathtub curves provide the key insight into the BER performance of the interface, which at the end of the day is what you really need to know as an engineer, whether you are working on parallel memory interfaces or serial links.
Grab a cup of coffee and watch the demonstration of our complete solution that uses channel simulation to perform BER analysis on DDR4 interfaces with Cadence Sigrity SystemSI - Parallel Bus. If you come from the SerDes space, a lot of this will look familiar to you, just as those new DDR4 specs probably do. But hey, as they say, what's old is new again. And just like before, Cadence is out in front. As a wise man once said, unless you're the lead dog of the sled team, the view doesn't change much.
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