currently i am designing a digital system in which the processor is clocking at a frequency of 50 MHz. Many 74HC series ICs are being used for the glue logic. The processor has also got the job of dealing with analog signals which are pre-processed using LM324 op- amp based buffers and switching circuits. For all these systems i have to use a common power bus.
How can i ensure the power bus integrity for this system. My constraint is that i have to use all through hole components.
where should i place the decoupling caps? what value they should be?can any one help me with any thumb rules in designing a decoupling network for this system?