Formal analysis in the sense of assertion based verification (not logic equivalence checking, which is also referred to as formal) can, in principle, be applied to any design. You will be constrained however by machine capacity, runtime and sometimes tool capabilities. The number one I'd pick for formal verification would be control logic. Its functionality, however large and complex, can often be described with a relatively straightforward set of properties and the runtimes in general are quite good. Another part where I like to employ formal is interface verification, for example AMBA busses. Cadence also offers assertion based verification IPs for AMBA protocols, developed for formal analysis. If you have some of your own protocols, they are often described in good protocol specs, which can often be translated into a very good set of properties.
I hope this helps a little.
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