Does anyone know how to define
string macros in Verilogams?
Today I have to do the
`define display_value(str, sig)
$display(“Value of signal %s is equal to %b”, str, sig)
If I place the following
macro in my code
The compiler translates to
$display(“Value of signal %s is
equal to %b”, “mysignal”, mysignal);
Unfortunately, it forces me to
duplicate information and maintain more code.
Ideally I would like a macro
that takes a single argument to create the signal name as well as its
respective content. Such as:
I wonder if there's a trick in verilogams to accomplish that.