I want to check interconnectivity among several IP blocks(in VHDL and Verilog) with PSL vunits. However I have a problem in binding. As I understand, i can bind the vunit to only one entity. But for interconnect check, I need port signals from both entities(IPs) so that I can continiously compare them. I can achieve this with SVA using SystemVerilog interfaces, but in PSL I am stuck.
Thanks for your help in advance,
The problem you face is likely how to specify out-of-module references. This can be done with nc_mirrors. This way you can "bind" to one entity but see any entity/module signal via the mirror call. That said, I did want to mention that Cadence has a pre-packaged verification app that addresses this problem directly. You can get more info on this verification app in a few ways
1) contact your local AE
2) watch a webinar about the solution: https://www.cadence.com/cadence/events/Pages/registration.aspx?eventid=516
3) review the Rapid Adoption Kit found on http://support.cadence.com. Under "Resources" you will see "Rapid Adoption Kits". Clicking the "SOC and IP level Functional Verification" link you see a kit for "SoC Connectivity Application"