Hi,Is anybody aware of an AHB verification component in system verilog similar to the AHB eVC in specman?I am not sure if there is one in cadence's verification component list.Thanks in advance.Rgds
Cadence is providing SystemVerilog enabled versions of the AHB (and other) eVCs.As you may be aware, Cadence has enhanced the eVC technology into a language neutral one called UVC - Universal Verification Components. These can be written in e, SystemVerilog, or SystemC, even a mixture of languages! Have a look at the IPCM documentation to see how it works.Talk to your local Cadence AE or sales guy about the SV enabled AHB UVC and they can help you.Regards,Steve.
Steve,Thanks for the information.I will talk with the local cadence AE.Rgds,Suresh