I am trying to synthesize a design using RTL compiler (Version v07.10-p004_1 (32-bit), built Jun 18 2007). The tool gives the following error information:
always @* begin
Error : Verilog-2001 feature. [VLOGPT-3] [read_hdl]
: Implicit event expression in file 'gcm.v' on line 199, column 9.
Is it because the RTL compiler version I used is too old?